CY7C09359AV-9AC Cypress Semiconductor Corp, CY7C09359AV-9AC Datasheet - Page 4

• Manufacturer Part Number: CY7C09359AV-9AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09359AV-9AC

• Density: 144Kb
• Access Time (max): 9ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 40MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 13b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 230mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Number Of Words: 8K
• Lead Free Status / RoHS Status: Not Compliant

Pin Definitions
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65 C to +150 C
Ambient Temperature with
Power Applied .............................................–55 C to +125 C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to V
DC Input Voltage......................................–0.5V to V
Notes:
4.
A
ADS
CE
CLK
CNTEN
CNTRST
I/O
LB
UB
OE
R/W
FT/PIPE
GND
NC
V
0L
CC
Left Port
L
0L
0L
L
L
Industrial parts are available in CY7C09359AV only.
–A
L
L
L
,CE
–I/O
12L
L
L
1L
L
17L
A
ADS
CE
CLK
CNTEN
CNTRST
I/O
LB
UB
OE
R/W
FT/PIPE
Right Port
0R
R
0R
0R
R
R
–A
R
R
R
–I/O
,CE
12R
R
R
1R
R
17R
Address Inputs (A
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during
normal read or write transactions. Asserting this signal LOW also loads the burst address
counter with data present on the I/O pins.
Chip Enable Input. To select either the left or right port, both CE
to their active states (CE
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respec-
tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte (I/O
the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
0
–I/O
0
–A
CC
CC
8
for x18, I/O
11
+0.5V
+0.5V
for 4K, A
0
0
–I/O
V
IL
4
and CE
15
0
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
Latch-Up Current ..................................................... >200 mA
Operating Range
0
–I/O
–A
Commercial
Industrial
for x16 devices).
12
7
Range
for x16) of the memory array. For read operations both
for 8K devices).
1
Description
V
[4]
IH
).
–40 C to +85 C
Temperature
0 C to +70 C
Ambient
0
AND CE
CY7C09349AV
CY7C09359AV
8/9L
1
must be asserted
–I/O
3.3V
3.3V
15/17L
V
CC
300 mV
300 mV
MAX
).
.
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