ISP1760BEGA STEricsson, ISP1760BEGA Datasheet - Page 17

• Manufacturer Part Number: ISP1760BEGA
• Manufacturer: STEricsson

Specifications of ISP1760BEGA

• Package Type: LQFP
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

CD00222702
Product data sheet
Fig 6.
USB BUS
Memory segmentation and access block diagram
AND LOW-SPEED)
USB HIGH-SPEED
TRANSACTION
TRANSLATOR
(FULL-SPEED
HOST AND
Table 4.
Memory map
ISO
INT
ATL
Payload
•
•
•
•
The address range of the internal RAM buffer is from 0400h to FFFFh.
The internal memory contains isochronous, interrupt and asynchronous PTDs, and
respective defined payloads.
All accesses to the internal memory are double word aligned.
Internal memory address range calculation:
Memory address = (CPU address − 0400h) (shift right >> 3). Base address is 0400h.
63 kB
address
data (64 bits)
Memory address
control signals
ARBITER
PAYLOAD
PAYLOAD
PTD32
PTD32
PTD32
PTD1
PTD2
PTD1
PTD2
PTD1
PTD2
240 MB/s
Rev. 08 — 13 April 2010
CPU address
0400h to 07FFh
0800h to 0BFFh
0C00h to 0FFFh
1000h to FFFFh
PAYLOAD
ASYNC
ISOCHRONOUS
INTERRUPT
MEMORY MAPPED
INPUT/OUTPUT,
MANAGEMENT
CONTROLLER
INTERRUPT
REGISTERS
SLAVE DMA
Embedded Hi-Speed USB host controller
CONTROL
MEMORY
UNIT,
AND
004aaa436
Memory address
0000h to 007Fh
0080h to 00FFh
0100h to 017Fh
0180h to 1FFFh
D[15:0]/D[31:0]
A[17:1]
DREQ
WR_N
DACK
RD_N
CS_N
IRQ
© ST-ERICSSON 2010. All rights reserved.
ISP1760
PROCESSOR
MICRO-
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