ISP1583ETUM STEricsson, ISP1583ETUM Datasheet - Page 60

• Manufacturer Part Number: ISP1583ETUM
• Manufacturer: STEricsson

Specifications of ISP1583ETUM

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 80.
ISP1583_7
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
DMA Burst Counter register: bit allocation
9.4.10 DMA Burst Counter register (address: 64h)
9.5.1 Interrupt register (address: 18h)
R/W
9.5 General registers
15
7
0
0
-
-
-
Table 80
Table 81.
The Interrupt register consists of 4 bytes. The bit allocation is given in
When a bit is set in the Interrupt register, it indicates that the hardware condition for an
interrupt has occurred. When the Interrupt register content is nonzero, the INT output will
be asserted corresponding to the Interrupt Enable register. On detecting the interrupt, the
external microprocessor must read the Interrupt register and mask it with the
corresponding bits in the Interrupt Enable register to determine the source of the interrupt.
Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various
bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset.
The DMA controller only has one interrupt bit: the source for a DMA interrupt is shown in
the DMA Interrupt Reason register (see
Bit
15 to 13
12 to 0
Fig 17. Programmable strobe timing
reserved
R/W
14
6
0
0
-
-
-
shows the bit allocation of the 2-byte register.
Symbol
-
BURSTCOUNTER
[12:0]
DMA Burst Counter register: bit description
R/W
13
5
0
0
-
-
-
Rev. 07 — 22 September 2008
BURSTCOUNTER[7:0]
Description
reserved
Burst Counter: This register defines the burst length. The
counter must be programmed to be a multiple of two in 16-bit
mode. The value of the burst counter must be programmed so
that the burst counter is a factor of the buffer size.
It is used to determine the assertion and deassertion of DREQ.
R/W
R/W
12
0
0
4
0
0
x
(N + 1) cycles
Table 72
R/W
R/W
x
11
0
0
3
0
0
BURSTCOUNTER[12:8]
and
Hi-Speed USB peripheral controller
004aaa125
Table
R/W
R/W
10
0
0
2
0
0
73).
R/W
R/W
9
0
0
1
1
1
Table
© NXP B.V. 2008. All rights reserved.
ISP1583
82.
R/W
R/W
8
0
0
0
0
0
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