LSI53C1030 LSI, LSI53C1030 Datasheet - Page 3

• Manufacturer Part Number: LSI53C1030
• Manufacturer: LSI

Specifications of LSI53C1030

• Lead Free Status / RoHS Status: Not Compliant

H A R D W A R E / S O F T W A R E O V E R V I E W
P C I - X I n t e r f a c e
Revision 2.2, and the PCI-X addendum, Revision 1.0. It implements a 133 MHz,
64-bit bus and is backward compatible with 33/66 MHz, 32/64-bit PCI.
Support for 64-bit addressing with Dual Address Cycle (DAC) is provided.
electrical load to the PCI bus. It uses one REQ/-GNT/ pair to arbitrate for
PCI bus mastership, and separate interrupt signals are generated for SCSI
Channel A and SCSI Channel B for maximum performance. The LSI53C1030
allows for independent control of the two channels; for example, RAID on one
channel and a legacy driver on the other. SCSI Interrupt Steering Logic (SISL)
provides alternate interrupt routing for RAID applications.
Specification Revision 1.1 and PC 99, as well as the draft PC2001. It
supports power states D0, D1, D2, D3hot and D3cold, power management
capabilities registers, and programmable values for PCI Subsystem Vendor
ID and Subsystem ID. Extended access cycles (Memory Read Line, Memory
Read Multiple, and Memory Write and Invalidate) are also supported.
S C S I C o r e s
on a single chip. Each controller supports wide Ultra320 SCSI synchronous
transfer rates up to 320 MBps on a LVD SCSI bus. Integrated LVDlink
transceivers support both LVD and single-ended signals with no external
transceivers required. Fast SCSI, Ultra SCSI, Ultra2 SCSI, Ultra160 SCSI,
and Ultra320 SCSI are all supported by the LSI53C1030 controller.
M e m o r y l n t e r f a c e s
through a parallel interface for add-in card designs. For ease of software
development and field upgrades of the ROM, the interface supports local
programming of FLASH memory. A serial 2-wire interface provides a
connection to a single external serial EEPROM for storing Subsystem Vendor
ID and Subsystem ID. No external SRAM is required for normal operation
of the device.
The host PCI-X interface complies with the PCI Local Bus Specification
The LSI53C1030 is a true PCI multifunction device and presents one
The LSI53C1030 complies with PCI Power Management Interface
The LSI53C1030 provides two independent Ultra320 SCSI controllers
The LSI53C1030 supports up to 4 MB of external expansion ROM
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F E A T U R E S ( C o n t i n u e d )
• SCSI Interrupt Steering Logic
• Proven integrated LVDlink
• Comprehensive SureLINK
• IEEE 1149.1 JTAG boundary scan
• Flash and local memory interface
• Packaged in a 456 EPBGA
• Supports Integrated Mirroring
• Supported by Fusion MPT drivers
– Enhanced interrupt coalescing
– Designed for optimal
(SISL) provides alternate interrupt
routing for RAID applications
transceivers for direct attach to
either Low Voltage Differential
(LVD) or single-ended (SE)
SCSI buses with precision-
controlled slew rates
domain validation
– Basic (Level 1) with inquiry
– Enhanced (Level 2) with
– Margined (Level 3) with
with full operating system support:
– Windows
– Linux
– Solaris
– UnixWare
– Novell
with hardware assist
packetized performance
command
read/write buffer
margining of drive strength
and slew rates
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NetWare
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NT
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/2000
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