STPCI2HEYCE STMicroelectronics, STPCI2HEYCE Datasheet - Page 48

• Manufacturer Part Number: STPCI2HEYCE
• Manufacturer: STMicroelectronics

Specifications of STPCI2HEYCE

• Lead Free Status / RoHS Status: Compliant

STPC® ATLAS
4.5.1. POWER ON SEQUENCE
Figure 4-2. CLK Timing Measurement Points
Figure 4-3
the STPC, also called cold reset.
There is no dependency between the different
power supplies and there is no constraint on their
rising time.
SYSRSTI# as no constraint on its rising edge but
must stay active until power supplies are all within
specifications,
recommended to let the STPC PLLs and strap
options stabilize.
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1
CLK
LEGEND:
NOTE; All sIgnals are sampled on the rising edge of the CLK.
V
V
V
Ref
IL (MAX)
IH (MIN)
describes the power-on sequence of
a
T1 - One Clock Cycle
T2 - Minimum Time at V
T3 - Minimum Time at V
T4 - Clock Fall Time
T5 - Clock Rise Time
T5
margin
T2
of 10µs
T1
IH
IL
is
even
T3
Strap Options are continuously sampled during
SYSRSTI# low and must remain stable. Once
SYSRSTI# is high, they MUST NOT CHANGE
until SYSRSTO# goes high.
Bus activity starts only few clock cycles after the
release of SYSRSTO#. The toggling signals
depend on the STPC configuration.
In ISA mode, activity is visible on PCI prior to the
ISA bus as the controller is part of the south
bridge.
In Local Bus mode, the PCI bus is not accessed
and the Flash Chip Select is the control signal to
monitor.
T4