STPCI2HEYCE STMicroelectronics, STPCI2HEYCE Datasheet - Page 50

• Manufacturer Part Number: STPCI2HEYCE
• Manufacturer: STMicroelectronics

Specifications of STPCI2HEYCE

• Lead Free Status / RoHS Status: Compliant

STPC® ATLAS
4.5.2 RESET SEQUENCE
Figure 4-4
STPC, also called warm reset.
The constraints on the strap options and the bus
activities are the same as for the cold reset.
The SYSRSTI# pulse duration must be long
enough to have all the strap options stabilized and
must be adjusted depending on resistor values.
Figure 4-4. Reset timing diagram
50/108
1
14 MHz
SYSRSTI#
ISACLK
Strap Options
HCLK
PCI_CLK
SYSRSTO#
describes the reset sequence of the
MD[63:0]
1.6 V
VALID CONFIGURATION
It is mandatory to have a clean reset pulse without
glitches as the STPC could then sample invalid
strap option setting and enter into an umpredicta-
ble mode.
While SYSRSTI# is active, the PCI clock PLL runs
in open loop mode at a speed of few 100’s KHz.
2.3 ms