STPCI2HEYCE STMicroelectronics, STPCI2HEYCE Datasheet - Page 96

• Manufacturer Part Number: STPCI2HEYCE
• Manufacturer: STMicroelectronics

Specifications of STPCI2HEYCE

• Lead Free Status / RoHS Status: Compliant

STPC® ATLAS
6.5.1. PCI INTERFACE
6.5.1.1. Introduction
In order to achieve a PCI interface which work at
clock
consideration has to be given to the timing of the
interface with all the various electrical and physical
constraints taken into consideration.
6.5.1.2. PCI Clocking Scheme
The PCI Clocking Scheme deserves a special
mention here. Basically the PCI clock (PCICLKO)
is generated on-chip from HCLK through a
programmable delay line and a clock divider. The
nominal frequency is 33MHz. This clock must be
looped to PCICLKI and goes to the internal South
Bridge through a deskewer. On the contrary, the
internal North Bridge is clocked by HCLK, putting
some additionnal constraints on T
96/108
frequencies
up
to
33MHz,
0
and T
1
.
careful
6.5.1.3. Board Layout Issues
The physical layout of the motherboard PCB
assumed in this presentation is as shown in
6-29. For the PCI interface, the most critical signal
is the clock. Any skew between the clocks at the
PCI components and the STPC will impact the
timing budget. In order to get well matched clocks
at all components it is recommended that all the
PCI clocks are individually driven from a serial
resistance with matched routing lengths. In other
words, all clock line lengths that go from the
resistor to the PCI chips (PCICLKx) must be
identical.
The figure below is for PCI devices soldered on-
board. In the case of a PCI slot, the wire length
must be shortened by 2.5" to compensate the
clock layout on the PCI board. The maximum clock
skew between all devices is 2ns according to PCI
specifications.
The
implementation. The exact timing constraints are
listed in the PCI section of the Electrical
Specifications Chapter.
Figure 6-30
describes a typical clock delay
Figure