MC9S08QD2CSC Freescale, MC9S08QD2CSC Datasheet - Page 53

• Manufacturer Part Number: MC9S08QD2CSC
• Manufacturer: Freescale

Specifications of MC9S08QD2CSC

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 4
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 4-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Program Memory Type: Flash
• Program Memory Size: 2KB
• Lead Free Status / RoHS Status: Compliant

5.5
Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine
(ISR), and then restore the CPU status so processing resumes where it was before the interrupt. Other than
the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events
such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI
under certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The
CPU will not respond until and unless the local interrupt enable is a 1 to enable the interrupt. The I bit in
the CCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset
which masks (prevents) all maskable interrupt sources. The user program initializes the stack pointer and
performs other system setup before clearing the I bit to allow the CPU to respond to interrupts.
When the CPU receives a qualified interrupt request, it completes the current instruction before responding
to the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequence as the SWI instruction
and consists of:
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of
another interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is
restored to 0 when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit
can be cleared inside an ISR (after clearing the status flag that generated the interrupt) so that other
interrupts can be serviced without waiting for the first service routine to finish. This practice is not
recommended for anyone other than the most experienced programmers because it can lead to subtle
program errors that are difficult to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR,
A, X, and PC registers to their pre-interrupt values by reading the previously saved information off the
stack.
When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced
first (see
Freescale Semiconductor
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Saving the CPU registers on the stack
Setting the I bit in the CCR to mask further interrupts
Fetching the interrupt vector for the highest-priority interrupt that is currently pending
Filling the instruction queue with the first three bytes of program information starting from the
address fetched from the interrupt vector locations
Table
Interrupts
For compatibility with M68HC08 devices, the H register is not
automatically saved and restored. It is good programming practice to push
H onto the stack at the start of the interrupt service routine (ISR) and restore
it immediately before the RTI that is used to return from the ISR.
5-2).
MC9S08QD4 Series MCU Data Sheet, Rev. 6
NOTE
Chapter 5 Resets, Interrupts, and General System Control
53