MC56F8006VLC Freescale, MC56F8006VLC Datasheet - Page 25

• Manufacturer Part Number: MC56F8006VLC
• Manufacturer: Freescale

Specifications of MC56F8006VLC

• Cpu Family: 56F8xxx
• Device Core Size: 16b
• Frequency (max): 32MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 2(18-chx12-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
(ANA4 and
CMP1_P2)
(GPIOD0)
(GPIOD1)
(GPIOD2)
(ANB12)
(ANB10)
(CMP0_
(CMP2_
(CMP2_
Signal
(TIN2)
Name
OUT)
OUT)
OUT)
TDO
(SS)
TCK
(T0)
TDI
SOIC
28
23
25
9
LQFP
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
32
30
32
14
LQFP
48
45
48
22
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2
Output
Analog
Output
Output
Output
Analog
Output
Output
Output
Analog
Output
Input/
Input/
Input/
Input/
Type
Input
Input
Input
Input
Input
Input
Input
tri-stated,
enabled
enabled
enabled
internal
Output,
internal
internal
During
Reset
pullup
pullup
pullup
Input,
Input,
State
Test Data Input — This input pin provides a serial input data stream
to the JTAG/EOnCE port. It is sampled on the rising edge of TCK
and has an on-chip pullup resistor.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANB12 — Analog input to channel 12 of ADCB
SS — SS is used in slave mode to indicate to the SPI module that
the current transfer is to be received.
TIN2 — Dual timer module channel 2 input.
CMP1_OUT — Analog comparator 1 output.
After reset, the default state is TDI.
Test Data Output — This three-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANB10 — Analog input to channel 10 of ADCB.
T0 — Dual timer module channel 0 input/output.
CMP2_OUT — Analog comparator 2 output.
After reset, the default state is TDO.
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pullup resistor. A
Schmitt-trigger input is used for noise immunity.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANA4 and CMP1_P2 — Analog input to channel 4 of ADCA and
positive input 2 of analog comparator 1.
CMP2_OUT — Analog comparator 2 output.
After reset, the default state is TCK.
Signal Description
Signal/Connection Descriptions
25