MC56F8006VLC Freescale, MC56F8006VLC Datasheet - Page 50

• Manufacturer Part Number: MC56F8006VLC
• Manufacturer: Freescale

Specifications of MC56F8006VLC

• Cpu Family: 56F8xxx
• Device Core Size: 16b
• Frequency (max): 32MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 2(18-chx12-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Lead Free Status / RoHS Status: Compliant

Specifications
8.7
50
1
2
3
4
oscillator (1 kHz)
clock monitoring
No output switching; all ports configured as inputs; all inputs low; no DC loads.
Low speed mode: LPR (lower voltage regulator control bit) = 0 and voltage regulator is in full regulation. Characterization only.
Low power mode: LPR (lower voltage regulator control bit) = 1; the voltage regulator is put into standby.
Partial power down mode: PPDE (partial power down enable bit) = 1; power management controller (PMC) enters partial
power down mode the next time that the STOP command is executed.
PPD with LP
PPD with no
PPD
1
2
LSstop
LPstop
enabled
XOSC
Mode
There is additional overhead that is part of the programming sequence. See the MC56F8006 Peripheral Reference
Manual for detail.
Specifies page erase time. There are 512 bytes per page in the program flash memory.
4
with
Flash Memory Characteristics
2
2
Mass erase time
Characteristic
Program time
200 kHz device clock;
relaxation oscillator (ROSC) in standby mode;
PLL disabled;
all peripheral modules disabled and clock gated off;
processor core in stop state.
32.768 kHz device clock;
Clocked by a 32.768 kHz external crystal relaxation
oscillator (ROSC) in power down;
PLL disabled;
all peripheral modules disabled and clock gated off;
processor core in stop state.
32.768 kHz clock fed on XTAL
RTC or COP monitoring XOSC (but no wakeup)
processor core in stop state
RTC or COP monitoring LP oscillator (but no
wakeup);
processor core in stop state.
RTC and LP oscillator are disabled;
processor core in stop state.
Erase time
2
1
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2
Conditions
Table 21. Supply Current Consumption
Table 22. Flash Timing Parameters
Symbol
t
t
erase
prog
t
me
Min
100
20
20
140.14 μA
36.72 μA
Typical @ 3.3 V, 25°C
3.39 μA
3.57 μA
TBD
I
DD
1
Typ
—
—
—
82.03 μA
2.45 μA
2.66 μA
0.5 μA
I
TBD
DDA
Max
40
—
—
Maximum @ 3.6 V, 25°C
Freescale Semiconductor
I
DD
—
—
—
—
—
1
Unit
ms
ms
μs
I
DDA
—
—
—
—
—