MC68HC908QT2CPE Freescale, MC68HC908QT2CPE Datasheet - Page 109

• Manufacturer Part Number: MC68HC908QT2CPE
• Manufacturer: Freescale

Specifications of MC68HC908QT2CPE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 6
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 4-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Package Type: PDIP
• Program Memory Type: Flash
• Program Memory Size: 1.5KB
• Lead Free Status / RoHS Status: Compliant

13.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the
configuration register 1 (CONFIG1). If the SSREC bit is a 1, then the stop recovery is reduced from the
normal delay of 4096 BUSCLKX4 cycles down to 32 BUSCLKX4 cycles. This is ideal for applications
using canned oscillators that do not require long start-up times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC cleared in the configuration
register 1 (CONFIG1).
13.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter (see
free-running after all reset states. See
internal reset recovery sequences.
13.6 Exception Control
Normal sequential program execution can be changed in three different ways:
13.6.1 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event.
Figure 13-7
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared).
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume.
interrupt entry timing.
Freescale Semiconductor
1. Interrupts
2. Reset
3. Break interrupts
a. Maskable hardware CPU interrupts
b. Non-maskable software interrupt instruction (SWI)
flow charts the handling of system interrupts.
Figure 13-9
MC68HC908QY/QT Family Data Sheet, Rev. 6
shows interrupt recovery timing.
13.4.2 Active Resets from Internal Sources
13.7.2 Stop Mode
for details.) The SIM counter is
for counter control and
Figure 13-8
Exception Control
shows
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