MCIMX287CVM4B Freescale, MCIMX287CVM4B Datasheet - Page 37

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MCIMX287CVM4B

Manufacturer Part Number
MCIMX287CVM4B
Description
Manufacturer
Freescale
Datasheet

Specifications of MCIMX287CVM4B

Lead Free Status / RoHS Status
Compliant

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Figure 13
figure.
3.4.5
The following timing specifications are given as a guide for a TPA that supports TRACECLK frequencies
up to 80 MHz.
3.4.5.1
This section describes TRACECLK timings.
Freescale Semiconductor
M16
M17
M18
M19
M20
M21
ENET0_TXD[1:0] (output)
ENET0_TX_EN
ENET0_RXD[1:0]
ID
ENET0_RX_ER
ENET_CLK (input)
ENET_CLK pulse width high
ENET_CLK pulse width low
ENET_CLK to ENET0_TXD[1:0], ENET0_TX_EN invalid
ENET_CLK to ENET0_TXD[1:0], ENET0_TX_EN valid
ENET0_RXD[1:0], CRS_DV(ENET0_RX_DV), ENET0_RX_ER to
ENET_CLK setup
ENET_CLK to ENET0_RXD[1:0], ENET0_RX_DV, ENET0_RX_ER hold
shows RMII mode timings.
CRS_DV (input)
Coresight ETM9 AC Interface Timing
TRACECLK Timing
i.MX28 Applications Processor Data Sheet for Consumer Products, Rev. 0
Figure 13. RMII Mode Signal Timing Diagram
Characteristic
Table 42
Table 42. RMII Signal Timing
M20
M18
describes the timing parameters (M16–M21) shown in the
M21
M19
M16
M17
Min.
35%
35%
3
2
2
Max.
65%
65%
12
ENET_CLK period
ENET_CLK period
Unit
ns
ns
ns
ns
37

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