MCIMX255AJM4A Freescale, MCIMX255AJM4A Datasheet - Page 42

• Manufacturer Part Number: MCIMX255AJM4A
• Manufacturer: Freescale

Specifications of MCIMX255AJM4A

• Lead Free Status / RoHS Status: Compliant

Figure 9
parameters (OW7–OW8) that are shown in the figure.
3.7.2
Table 33
implementation of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew.
42
OW5
OW6
OW7
OW8
OW9
ID
ID
and
shows parameters used to specify the ATA timing. These parameters depend on the
Write 0 Low Time
Transmission Time Slot
Write 1 / read low time
Transmission time slot
Release time
ATA Timing Parameters
Figure 10
1-Wire bus
(OWIRE_LINE)
1-Wire bus
(OWIRE_LINE)
show write 1 and read sequence timing, respectively.
i.MX25 Applications Processor for Automotive Products, Rev. 4
Parameter
Parameter
Table 31. WR0 Sequence Timing Parameters
Figure 9. Write 1 Sequence Timing Diagram
Figure 10. Read Sequence Timing Diagram
Table 32. WR1 /RD Timing Parameters
OW7
OW7
OW9
t
t
Symbol
Symbol
RELEASE
WR0_low
t
t
t
LOW1
SLOT
SLOT
OW8
OW8
OW5
Min.
Min.
60
15
60
1
Table 32
Typ.
117
Typ.
100
117
—
5
Freescale Semiconductor
describes the timing
Max.
Max.
120
120
120
15
45
Units
Units
s
s
s
s
s