MC9328MXLVP20 Freescale, MC9328MXLVP20 Datasheet

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... Freescale Semiconductor Advance Information MC9328MXL 1 Introduction © Freescale Semiconductor, Inc., 2004. All rights reserved. This document contains information on a new product. Specifications and information herein are subject to change without notice. MC9328MXL/D Rev. 5.1, 11/2004 MC9328MXL Package Information Plastic Package (MAPBGA–225 or 256) ...

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... ARM9TDMI™ I Cache D Cache Interrupt AIPI 1 VMMU Controller DMAC Bus AIPI 2 (11 Chnl) Control EIM & SDRAMC MC9328MXL Advance Information, Rev. 5.1 Standard System I/O GPIO PWM Timer 1 & 2 RTC Watchdog Multimedia Multimedia Accelerator Video Port Human Interface LCD Controller Freescale Semiconductor ...

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... Features 1.3 Target Applications Freescale Semiconductor MC9328MXL Advance Information, Rev. 5.1 Introduction 3 ...

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... Introduction 1.4 Revision History Table 1. MC9328MXL Data Sheet Revision History Changes references from Motorola to Freescale Semiconductor as applicable, throughout document. 4 Revision MC9328MXL Advance Information, Rev. 5.1 Freescale Semiconductor ...

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... Table 2. MC9328MXL Ordering Information Temperature Solderball Type - Standard Pb-free Standard Pb-free O O Standard - Pb-free O O Standard - Pb-free Standard Pb-free Standard - Pb-free MC9328MXL Advance Information, Rev. 5.1 Introduction Order Number MC9328MXLCVH15(R2) MC9328MXLCVM15(R2) MC9328MXLVH20(R2) MC9328MXLVM20(R2) MC9328MXLDVH20(R2) MC9328MXLDVM20(R2) MC9328MXLCVF15(R2) MC9328MXLCVP15(R2) MC9328MXLVF20(R2) MC9328MXLVP20(R2) MC9328MXLDVF20(R2) MC9328MXLDVP20(R2) 5 ...

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... SDRAM data enable CSD0 SDRAM/SyncFlash Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable by programming the system control register. 6 Table 3. MC9328MXL Signal Descriptions Function/Notes External Bus/Chip-Select (EIM) Bootstrap SDRAM Controller MC9328MXL Advance Information, Rev. 5.1 Freescale Semiconductor ...

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... driven logic-low at reset, the external chip-select space will be configured to big endian. External DMA request pin. ETMTRACESYNC ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode. Freescale Semiconductor Function/Notes Clocks and Resets JTAG DMA ETM MC9328MXL Advance Information, Rev ...

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... Please refer to the SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. 8 Function/Notes CMOS Sensor Interface LCD Controller SPI 1 and 2 MC9328MXL Advance Information, Rev. 5.1 Freescale Semiconductor ...

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... General purpose Input0—Can be used for Memory Stick Insertion/Extraction detect MS_PI1 General purpose Input1—Can be used for Memory Stick Insertion/Extraction detect UART1_RXD Receive Data UART1_TXD Transmit Data Freescale Semiconductor Function/Notes General Purpose Timers USB Device Secure Digital Interface Memory Stick Interface UARTs – IrDA/Auto-Bauding MC9328MXL Advance Information, Rev ...

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... AVSS Quiet ground for analog blocks QVDD Power supply pins for silicon internal circuitry QVSS Ground pins for silicon internal circuitry 10 Function/Notes PWM Digital Supply Pins Supply Pins – Analog Modules Internal Power Supply MC9328MXL Advance Information, Rev. 5 protocol) Freescale Semiconductor ...

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... SGND Ground routed through substrate of package; not to be bonded 3 Specifications 3.1 Maximum Ratings Rating Supply voltage Maximum operating temperature range MC9328MXLVH20/MC9328MXLVM20/ MC9328MXLVF20/MC9328MXLVP20 Maximum operating temperature range MC9328MXLDVH20/MC9328MXLDVM20/ MC9328MXLDVF20/MC9328MXLDVP20 Maximum operating temperature range MC9328MXLCVH15/MC9328MXLCVM15/ MC9328MXLCVF15/MC9328MXLCVP15 ESD at human body model (HBM) ESD at machine model (MM) ...

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... MC9328MXL Advance Information, Rev. 5.1 Symbol Minimum Maximum NVDD 2.70 3.30 NVDD 1.70 3.30 QVDD 1.70 1.90 QVDD 1.80 2.00 AVDD 1.70 3.30 Min Typical Max – QVDD at – 1.8v = 120mA; NVDD+AVDD at 3.0v = 30mA – 25 – – 45 – – 35 – Freescale Semiconductor Unit Unit ...

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... DD C Input capacitance i C Output capacitance‘ o 3.5 AC Electrical Characteristics TRISTATE Time from TRISTATE activate until I/O becomes Hi-Z EXTAL32k input jitter (peak to peak) Freescale Semiconductor Parameter 2.0 mA -2.5 mA) = 1.8V) Table 7. Tristate Signal Timing Table 8. 32k/16M Oscillator Signal Timing – MC9328MXL Advance Information, Rev. 5.1 ...

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... Figure 2. Trace Port Timing Diagram 1.8V ± 0.10V Minimum Maximum 0 85 1.3 – 3 – MC9328MXL Advance Information, Rev. 5.1 – – ms TBD TBD – – – – Valid Data 3.0V ± 0.30V Unit Minimum Maximum 0 100 MHz 2 – – ns Freescale Semiconductor ...

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... Table 9. Trace Port Timing Diagram Parameter Table (Continued) Ref Parameter No. 3a Clock rise time 3b Clock fall time 4a Output hold time 4b Output setup time Freescale Semiconductor 1.8V ± 0.10V Minimum Maximum – 4 – 3 2.28 – 3.42 – MC9328MXL Advance Information, Rev. 5.1 Specifications 3.0V ± ...

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... Ps) 300 350 400 (70 Ps) 270 320 370 (64 Ps) – 0.005 0.01 (0.01%) – 1.0 1.5 (10%) 1.7 – 2.5 – – 4 Freescale Semiconductor Unit MHz MHz MHz – – – – – P sec T ref T ref T ref T ref 2•T dck ...

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... Reset Module 90% AVDD Freescale Semiconductor NOTE: 10% AVDD Exact 300ms Figure 3. Timing Relationship with POR MC9328MXL Advance Information, Rev. 5.1 Specifications 7 cycles @ CLK32 14 cycles @ CLK32 17 ...

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... Min 1 note 300 MC9328MXL Advance Information, Rev. 5.1 14 cycles @ CLK32 3.0V ± 0.30V Unit Max Min Max – 1 – – note 300 300 300 Cycles of CLK32 Cycles of CLK32 – 4 – Cycles of CLK32 Cycles of CLK32 Freescale Semiconductor ...

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... EB (falling edge) LBA (negated falling edge) LBA (negated rising edge) Burst Clock (rising edge) Burst Clock (falling edge) Read Data Write Data (negated falling) Write Data (negated rising) Freescale Semiconductor Figure 5. EIM Bus Timing Diagram MC9328MXL Advance Information, Rev. 5.1 Specifications 19 ...

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... Freescale Semiconductor ...

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... The max n is 1022 the system clock period (system clock is 96 MHz). 3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state. Freescale Semiconductor Table 13. Access Cycle Timing Parameters 1.8V ± 0.10V Min – ...

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... T is the system clock period (system clock is 96 MHz). 3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state. 22 Table 14. Access Cycle Timing Parameters 1.8V ± 0.10V Min 0 MC9328MXL Advance Information, Rev. 5.1 3.0V ± 0.30V Unit Max Min Max – 0 – Freescale Semiconductor ns ...

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... EIM External Bus Timing Seq/Nonseq Last Valid Address Freescale Semiconductor Read V1 Last Valid Data Read Figure 8. WSC = 1, A.HALF/E.HALF MC9328MXL Advance Information, Rev. 5.1 Specifications ...

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... Specifications Nonseq Write Last Valid Data Last Valid Address Figure 9. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF 24 V1 Write Data (V1) Last Valid Data Last Valid Data MC9328MXL Advance Information, Rev. 5.1 Unknown V1 Write Write Data (V1) Freescale Semiconductor ...

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... Nonseq Last Valid Addr Figure 10. WSC = 1, OEA = 1, A.WORD/E.HALF Freescale Semiconductor Read V1 Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Advance Information, Rev. 5.1 Specifications V1 Word Address 2/2 Half Word 25 ...

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... Specifications Nonseq Write V1 Last Valid Data Last Valid Addr Figure 11. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF 26 Write Data (V1 Word) Last Valid Data Address V1 1/2 Half Word MC9328MXL Advance Information, Rev. 5.1 Address Write 2/2 Half Word Freescale Semiconductor ...

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... Nonseq Read V1 Last Valid Addr Figure 12. WSC = 3, OEA = 2, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Advance Information, Rev. 5.1 Specifications V1 Word Address 2/2 Half Word 27 ...

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... Specifications Nonseq Write V1 Last Valid Data Last Valid Addr Last Valid Data Figure 13. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF 28 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Advance Information, Rev. 5.1 Address 2/2 Half Word Freescale Semiconductor ...

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... Nonseq Read V1 Last Valid Addr Figure 14. WSC = 3, OEA = 4, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Advance Information, Rev. 5.1 Specifications V1 Word Address 2/2 Half Word 29 ...

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... Specifications Nonseq Write V1 Last Valid Data Last Valid Addr Last Valid Data Figure 15. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF 30 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Advance Information, Rev. 5.1 Address 2/2 Half Word Freescale Semiconductor ...

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... Nonseq Read V1 Last Valid Addr Figure 16. WSC = 3, OEN = 2, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Advance Information, Rev. 5.1 Specifications V1 Word Address 2/2 Half Word 31 ...

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... Specifications Nonseq Read V1 Last Valid Addr Figure 17. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF 32 Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Advance Information, Rev. 5.1 V1 Word Address 2/2 Half Word Freescale Semiconductor ...

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... Nonseq Write V1 Last Valid Data Last Valid Addr Last Valid Data Figure 18. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Advance Information, Rev. 5.1 Specifications Unknown Address 2/2 Half Word ...

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... Specifications Nonseq Write V1 Last Valid Data Last Valid Addr Last Valid Data Figure 19. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF 34 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Advance Information, Rev. 5.1 Unknown Address 2/2 Half Word Freescale Semiconductor ...

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... Nonseq Read V1 Last Valid Data Last Valid Addr Figure 20. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF Freescale Semiconductor Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MXL Advance Information, Rev. 5.1 Specifications Write Data Read Data Address V8 Write Write Data ...

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... Last Valid Data Last Valid Addr Figure 21. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF 36 Read Idle Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MXL Advance Information, Rev. 5.1 Write Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... Nonseq Write V1 Last Valid Data Last Valid Addr Last Valid Data Figure 22. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF Freescale Semiconductor Write Data (Word) Last Valid Data Address V1 Write Write Data (1/2 Half Word) MC9328MXL Advance Information, Rev. 5.1 Specifications Address Write Data (2/2 Half Word) ...

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... Specifications Nonseq Read V1 Last Valid Addr Figure 23. WSC = 3, CSA = 1, A.HALF/E.HALF 38 Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MXL Advance Information, Rev. 5.1 Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... Nonseq Read V1 Last Valid Data Last Valid Figure 24. WSC = 2, OEA = 2, CNC = 3, BCM = 0, A.HALF/E.HALF Freescale Semiconductor Idle Seq Read V2 Read Data (V1) Address V1 CNC Read Read Data (V1) MC9328MXL Advance Information, Rev. 5.1 Specifications Read Data (V2) Address V2 Read Data (V2) 39 ...

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... Last Valid Data Last Valid Addr Figure 25. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF 40 Idle Nonseq Write V8 Last Valid Data Address V1 CNC Read Read Data Last Valid Data MC9328MXL Advance Information, Rev. 5.1 Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... Nonseq Read V1 Last Valid Addr Figure 26. WSC = 3, SYNC = 1, A.HALF/E.HALF Freescale Semiconductor Nonse Read V5 Address V1 Read V1 Word V2 Word MC9328MXL Advance Information, Rev. 5.1 Specifications Idle Address V5 V5 Word V6 Word 41 ...

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... Specifications Nonseq Read V1 Last Valid Data Last Valid Addr Figure 27. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD 42 Seq Seq Read Read Word V2 Word Address V1 Read V1 Word V2 Word MC9328MXL Advance Information, Rev. 5.1 Idle Seq Read V4 V3 Word V4 Word V3 Word V4 Word Freescale Semiconductor ...

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... Nonseq Read V1 Last Valid Data Last Valid Figure 28. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF Freescale Semiconductor Seq Read V2 V1 Word Address V1 Read V1 1/2 V1 2/2 MC9328MXL Advance Information, Rev. 5.1 Specifications Idle V2 Word Address V2 V2 1/2 V2 2/2 43 ...

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... Specifications Non seq Read V1 Last Figure 29. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF 44 Last Valid Data Address V1 Read V1 1/2 MC9328MXL Advance Information, Rev. 5.1 Idle Seq Read V2 V1 Word V2 Word V1 2/2 V2 1/2 V2 2/2 Freescale Semiconductor ...

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... Non seq Read V1 Last Figure 30. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read V1 1/2 MC9328MXL Advance Information, Rev. 5.1 Specifications Idle Seq Read V2 V1 Word V2 Word V1 2/2 V2 1/2 V2 2/2 45 ...

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... Figure 32. Master SPI Timing Diagram Using SPI_RDY Level Trigger SS (output) SCLK, MOSI, MISO Figure 33. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger SS (input) SCLK, MOSI, MISO Figure 34. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT 46 MC9328MXL Advance Information, Rev. 5.1 Freescale Semiconductor ...

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... SS input pulse width CSPI system clock period (PERCLK2). 2. Tsclk = Period of SCLK. 3. WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register. 3.11 LCD Controller LSCLK LD[15:0] Freescale Semiconductor 1.8V ± 0.10V Minimum Maximum 1 – – 3 • Tsclk 2 • Tsclk – ...

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... Maximum Minimum – 2 Non-display region XMAX T8 T9 T10 Minimum Corresponding Register Value T5+T6 +T7+T9 XMAX MC9328MXL Advance Information, Rev. 5.1 3.0V ± 0.30V Unit Maximum – Display region T7 Unit (VWAIT1·T2)+T5+T6+T7+T9 XMAX+T5+T6+T7+T9+T10 VWIDTH·(T2) VWAIT2·(T2) HWIDTH+1 HWAIT2+1 Freescale Semiconductor ...

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... The polarity of SCLK and LD[15:0] can also be programmed. • SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 37, SCLK is always active. • For T9 non-display region, VSYN is non-active used as an reference. • XMAX is defined in pixels. Freescale Semiconductor Minimum Corresponding Register Value MC9328MXL Advance Information, Rev ...

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... MC9328MXL Advance Information, Rev. 5.1 Valid Data Valid Data 3.0 ± 0.30V Unit Minimum Maximum 0 25/5 MHz 0 400 kHz 10/50 – 10/50 – – 10/50 3 – 10/50 3 5/5 – 5/5 – 5/5 – 5/5 – Freescale Semiconductor ...

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... Table 19. State Signal Parameters for Figure 39 through Figure 43 Card Active Symbol Z High impedance state D * CRC Cyclic redundancy check bits (7 bits) CMD S T CMD S T Figure 39. Timing Diagrams at Identification Mode Freescale Semiconductor Definition Symbol S Data bits T Repetition cycles ID Host Command Content CRC ...

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... Command response timing (data transfer mode) N cycles RC Response ****** CRC Timing response end to next CMD start (data transfer mode) N cycles CC ****** CRC Timing of command sequences (all modes) MC9328MXL Advance Information, Rev. 5.1 Response Content CRC Host Command Content CRC Host Command Content CRC Freescale Semiconductor ...

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... CMD S T DAT Host Command CMD Content CRC S T DAT Z****Z CMD S T DAT Freescale Semiconductor N cycles CR Host Command Content ****** CRC Z**** ****** cycles AC Timing of single block read N cycles CR Response ****** Content CRC ****** ***** Read Data N cycles AC N cycles CR Host Command Content ****** CRC ***** Timing of stop command ...

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N cycles CR Host Command CMD S T Content CRC ****** DAT Z****Z DAT Z****Z Timing of the block write command CMD DAT Content Status ...

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N cycles CR Host Command CMD Content CRC ****** DAT Write Data Busy ...

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... Command read cycle cycles Clock Command-command cycle cycles Clock Command write cycle cycles Clock Stop transmission cycle cycles TAAC: Data read access time -1 defined in CSD register bit[119:112] NSAC: Data read access time -2 in CLK cycles (NSAC·100) defined in CSD register bit[111:104] Freescale Semiconductor ...

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... Interrupt Period For 4-bit DAT[1] For 1-bit CMD ****** DAT[1] S Block Data For 4-bit DAT[2] S Block Data For 4-bit 3.13 Memory Stick Host Controller Freescale Semiconductor Response Block Data Interrupt Period Figure 44. SDIO IRQ Timing Diagram CMD52 CRC Figure 45. SDIO ReadWait Timing Diagram MC9328MXL Advance Information, Rev ...

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... MS_SCLKO low pulse width 1 9 MS_SCLKO rise time 1 10 MS_SCLKO fall time Figure 46. MSHC Signal Timing Diagram Parameter 1 1 MC9328MXL Advance Information, Rev. 5 3.0 ± 0.3V Unit Minimum Maximum – 25 MHz 20 – – ns – – – 25 MHz 20 – – ns – – Freescale Semiconductor ...

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... SDIO pin when the pin direction changes the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge. Freescale Semiconductor Parameter 1,2 MC9328MXL Advance Information, Rev. 5.1 Specifications 3.0 ± 0.3V ...

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... SDRAM Controller 60 Figure 47. PWM Output Timing Diagram ± 3.3 – 7.5 – – 5 – 6.67 5.7 – 5.7 – MC9328MXL Advance Information, Rev. 5.1 3.0V ± 0.30V Minimum Maximum 0 100 MHz 5/10 – ns 5/10 – ns – 5/10 ns – 5/ – – ns Freescale Semiconductor ...

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... Figure 48. SDRAM/SyncFlash Read Cycle Timing Diagram 1 SDRAM clock high-level width 2 SDRAM clock low-level width 3 SDRAM clock cycle time 3S CS, RAS, CAS, WE, DQM setup time Freescale Semiconductor COL/BA Data Note: CKE is high during the read/write cycle. Table 23. SDRAM Timing Parameter Table ± 0.10V 2.67 6 11.4 3 ...

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... RCD MC9328MXL Advance Information, Rev. 5.1 3.0V ± 0.30V Minimum Maximum – 2 – – 3 – – 2 – 6.84 – 6 6.84 – – 22 – 2.5 – 6.84 – 6 6.84 – – 22 – – RCD Freescale Semiconductor ...

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... Figure 49. SDRAM/SyncFlash Write Cycle Timing Diagram Table 24. SDRAM Write Timing Parameter Table 1 SDRAM clock high-level width 2 SDRAM clock low-level width 3 SDRAM clock cycle time 4 Address setup time 5 Address hold time 6 Precharge cycle period 7 Active to read/write command delay Freescale Semiconductor 6 ROW/BA ± 0.10V 2.67 6 11.4 3.42 2. RCD MC9328MXL Advance Information, Rev ...

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... Table 25. SDRAM Refresh Timing Parameter Table 1 SDRAM clock high-level width 2 SDRAM clock low-level width 64 ± 0.10V 4.0 – 2.28 – 6 ± 0.10V 2.67 – 6 – MC9328MXL Advance Information, Rev. 5.1 3.0V ± 0.30V Minimum Maximum 2 – – ns 3.0V ± 0.30V Minimum Maximum 4 – – ns Freescale Semiconductor ...

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... SDRAM clock cycle time. These settings can be found in the MC9328MXL reference RP RC manual. SDCLK CS RAS CAS WE ADDR BA DQ DQM CKE Figure 51. SDRAM Self-Refresh Cycle Timing Diagram Freescale Semiconductor ± 0.10V 11.4 – 3.42 – 2.28 – – – MC9328MXL Advance Information, Rev. 5.1 Specifications 3.0V ± ...

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... USBD_VPO low USBD_ROE active to ROE_VMO USBD_VMO high USBD_VPO high to VPO_ROE USBD_ROE deactivated PERIOD 2 ± 0.10V 83.14 83.47 81.55 81.98 83.54 83.80 MC9328MXL Advance Information, Rev. 5 VMO_ROE 3 t VPO_ROE t FEOPT 5 3.0V ± 0.30V Minimum Maximum 83.14 83.47 ns 81.55 81.98 ns 83.54 83.80 ns Freescale Semiconductor ...

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... Figure 53. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX) Table 27. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX) Ref No. Parameter Receiver SE0 interval of EOP FEOPR Freescale Semiconductor ± 0.10V 248.90 249.13 160.00 175.00 11.97 12.03 1.8V ± 0.10V ...

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... Figure 54. Definition of Bus Timing for I 2 Table 28 Bus Timing Parameter Table ± 182 0 11.4 80 480 182.4 MC9328MXL Advance Information, Rev. 5 3.0V ± 0.30V Minimum Maximum – 160 – 171 0 150 – 10 – – 120 – – 320 – – 160 – Freescale Semiconductor ...

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... STFS (wl) Output STXD Output SRXD Input Note: SRXD input in synchronous mode only. Figure 55. SSI Transmitter Internal Clock Timing Diagram SRCK Output SRFS (bl) Output SRFS (wl) Output SRXD Input Figure 56. SSI Receiver Internal Clock Timing Diagram Freescale Semiconductor MC9328MXL Advance Information, Rev. 5.1 Specifications 69 ...

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... Table 29. SSI (Port C Primary Function) Timing Parameter Table 1 STCK/SRCK clock period 2 STCK high to STFS (bl) high 3 SRCK high to SRFS (bl) high 70 ± – 3 1.5 4.5 3 -1.2 -1.7 MC9328MXL Advance Information, Rev. 5.1 3.0V ± 0.30V Minimum Maximum 83.3 – ns 1.3 3.9 ns -1.1 -1.5 ns Freescale Semiconductor ...

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... STCK high to STFS (wl) high 23 SRCK high to SRFS (wl) high 24 STCK high to STFS (wl) low 25 SRCK high to SRFS (wl) low 26 STCK high to STXD valid from high impedance 27a STCK high to STXD high 27b STCK high to STXD low Freescale Semiconductor ± 3 2.5 4.3 3 0.1 -0.8 3 1.48 4.45 3 -1.1 -1 ...

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... Minimum Maximum 2 ) 83.3 – 1.5 4.2 -0.1 1.0 2.7 4.6 1.1 2.0 1.5 4.2 -0.1 1.0 2.7 4.6 Freescale Semiconductor ...

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... STCK high to STXD valid from high impedance 27a STCK high to STXD high 27b STCK high to STXD low 28 STCK high to STXD high impedance 29 SRXD setup time before SRCK low 30 SRXD hold time after SRCK low Freescale Semiconductor ± 3 1.25 2.28 14.93 16.19 1.25 3.42 2.51 3.99 12.43 14 ...

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... SSI module selects the input based on FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function bit length word length. 74 ± 18.81 – 0 – 1.14 – 0 – MC9328MXL Advance Information, Rev. 5.1 3.0V ± 0.30V Minimum Maximum 2 ) 16.5 – – ns 1.0 – – ns Freescale Semiconductor ...

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... CMOS Sensor Interface u 3.19.1 Gated Clock Mode VSYNC HSYNC PIXCLK DATA[7:0] Figure 59. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge Freescale Semiconductor Valid Data Valid Data MC9328MXL Advance Information, Rev. 5.1 Specifications u Valid Data 75 ...

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... Valid Data Valid Data 180 10.42 10.42 0 MC9328MXL Advance Information, Rev. 5.1 Valid Data – ns – ns – ns – ns – ns – MHz Freescale Semiconductor ...

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... Non-Gated Clock Mode VSYNC PIXCLK DATA[7:0] Figure 61. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge Freescale Semiconductor Valid Data Valid Data MC9328MXL Advance Information, Rev. 5.1 Specifications Valid Data 77 ...

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... Table 32. Non-Gated Clock Mode Parameters 1 csi_vsync to csi_pixclk 2 csi_d setup time 3 csi_d hold time 4 csi_pixclk high time 5 csi_pixclk low time 6 csi_pixclk frequency 78 Valid Data Valid Data 180 1 1 10.42 10.42 0 MC9328MXL Advance Information, Rev. 5.1 Valid Data – ns – ns – ns – ns – MHz Freescale Semiconductor ...

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Pin-Out and Package Information NVSS1 DAT3 CLK NVSS4 USBD_ AFE B A24 DAT1 CMD SSI1_RXDAT USBD_ ROE C A23 D31 DAT0 SSI1_RXCLK USBD_ RCV D A22 D30 D29 SSI1_RXFS USBD_ SUSPND E A20 ...

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A CMD SSI1_ SSI1_ USBD_ USBD_ RXCLK TXCLK ROE SUSPND B DAT3 CLK SSI1_ USBD_ USBD_RCV RXDAT AFE C D31 DAT0 SSI1_ SSI1_ DAT2 RXFS TXFS D A23 A24 DAT1 SSI1_ NVDD1 TXDAT E A21 A22 ...

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... INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. Figure 63. MC9328MXL 256 MAPBGA Mechanical Drawing Freescale Semiconductor Case Outline 1367 MC9328MXL Advance Information, Rev. 5.1 Pin-Out and Package Information SIDE VIEW 81 ...

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... MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. Figure 64. MC9328MXL 225 PBGA Mechanical Drawing 82 Case Outline 1304B MC9328MXL Advance Information, Rev. 5.1 SIDE VIEW Freescale Semiconductor ...

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... Freescale Semiconductor NOTES MC9328MXL Advance Information, Rev. 5.1 83 ...

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... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...