MC9328MXLVP20 Freescale, MC9328MXLVP20 Datasheet - Page 7

• Manufacturer Part Number: MC9328MXLVP20
• Manufacturer: Freescale

Specifications of MC9328MXLVP20

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
CSD1
RAS
CAS
SDWE
SDCKE0
SDCKE1
SDCLK
RESET_SF
EXTAL16M
XTAL16M
EXTAL32K
XTAL32K
CLKO
RESET_IN
RESET_OUT
POR
TRST
TDO
TDI
TCK
TMS
BIG_ENDIAN
ETMTRACESYNC
Signal Name
SDRAM/SyncFlash Chip-select signal which is multiplexed with CS3 signal. These two signals are
selectable by programming the system control register. By default, CSD1 is selected, so it can be
used as SyncFlash boot chip-select by properly configuring BOOT [3:0] input pins.
SDRAM/SyncFlash Row Address Select signal
SDRAM/SyncFlash Column Address Select signal
SDRAM/SyncFlash Write Enable signal
SDRAM/SyncFlash Clock Enable 0
SDRAM/SyncFlash Clock Enable 1
SDRAM/SyncFlash Clock
SyncFlash Reset
Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is
shut down.
Crystal output
32 kHz crystal input
32 kHz crystal output
Clock Out signal selected from internal clock signals.
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all
modules (except the reset module and the clock control module) are reset.
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from
the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally
generated by an external RC circuit designed to detect a power-up event.
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
Serial Output for test instructions and data. Changes on the falling edge of TCK.
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
Test Clock to synchronize test logic and control register access through the JTAG port.
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge
of TCK.
Big Endian—Input signal that determines the configuration of the external chip-select space. If it is
driven logic-high at reset, the external chip-select space will be configured to little endian. If it is
driven logic-low at reset, the external chip-select space will be configured to big endian.
External DMA request pin.
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
Table 3. MC9328MXL Signal Descriptions (Continued)
MC9328MXL Advance Information, Rev. 5.1
Clocks and Resets
JTAG
DMA
ETM
Function/Notes
Signals and Connections
7