MC9328MX21VG Freescale, MC9328MX21VG Datasheet - Page 8

• Manufacturer Part Number: MC9328MX21VG
• Manufacturer: Freescale

Specifications of MC9328MX21VG

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Descriptions
8
referred to as HSYNC)
LP_HSYNC (or simply
SLCDC1_DAT[15:0] SLCDC Data output signals for connection to a parallel SLCD panel interface. These signals are
(or simply referred
SLCDC1_CLK
SLCDC2_CLK
to as VSYNC)
Signal Name
FLM_VSYNC
SLCDC1_CS
SLCDC1_RS
SLCDC2_CS
SLCDC2_RS
CSI_HSYNC
CSI_PIXCLK
SLCDC1_D0
CSI_VSYNC
CONTRAST
SPL_SPR
LD [17:0]
OE_ACD
LSCLK
REV
CLS
PS
Sensor port vertical sync
Sensor port horizontal sync
Sensor port data latch clock
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. LD[15:0] signals are
multiplexed with SLCDC1_DAT[15:0] from SLCDC1 and BMI_D[15:0]. LD[17] signal is multiplexed with
BMI_WRITE of BMI. LD[16] is multiplexed with BMI_READ_REQ of BMI and EXT_DMAGRANT.
Frame Sync or Vsync—This signal also serves as the clock signal output for gate
driver (dedicated signal SPS for Sharp panel HR-TFT). This signal is multiplexed with BMI_RXF_FULL
and BMI_WAIT of the BMI.
Line Pulse or HSync
Shift Clock. This signal is multiplexed with the BMI_CLK_CS from BMI.
Alternate Crystal Direction/Output Enable.
This signal is used to control the LCD bias voltage as contrast control. This signal is multiplexed with the
BMI_READ from BMI.
Sampling start signal for left and right scanning. This signal is multiplexed with the SLCDC1_CLK.
Control signal output for source driver (Sharp panel dedicated signal). This signal is multiplexed with the
SLCDC1_CS.
Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated signal). This
signal is multiplexed with the SLCDC1_RS.
Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This signal is
multiplexed with SLCDC1_D0.
SLCDC Clock output signal. This signal is multiplexed and available at 2 alternate locations. These are
SPL_SPR and SD2_CLK signals of LCDC and SD2, respectively.
SLCDC Chip Select output signal. This signal is multiplexed and available at 2 al t ernate signal locations.
These are PS and SD2_CMD signals of LCDC and SD2, respectively.
SLCDC Register Select output signal. This signal is multiplexed and available at 2 alternate signal
locations. These are CLS and SD2_D3 signals of LCDC and SD2, respectively.
SLCDC serial data output signal. This signal is multiplexed and available at 2 alternate signal locations.
These are and REV and SD2_D2 signals of LCDC and SD2, respectively. This signal is inactive when a
parallel data interface is used.
multiplexed with LD[15:0] while an alternate 8-bit SLCD muxing is available on LD[15:8]. Further
alternate muxing of these signals are available on some of the USB OTG and USBH1 signals.
SLCDC Clock input signal for pass through to SLCD device. This signal is multiplexed with SSI3_CLK
signal from SSI3.
SLCDC Chip Select input signal for pass through to SLCD device. This signal is multiplexed with
SSI3_TXD signal from SSI3.
SLCDC Register Select input signal for pass through to SLCD device. This signal is multiplexed with
SSI3_RXD signal from SSI3.
Table 2. i.MX21 Signal Descriptions (Continued)
MC9328MX21 Technical Data, Rev. 3.4
Smart LCD Controller
LCD Controller
Function/Notes
Freescale Semiconductor