IP-POSPHY/L3 Altera, IP-POSPHY/L3 Datasheet - Page 6

• Manufacturer Part Number: IP-POSPHY/L3
• Manufacturer: Altera

Specifications of IP-POSPHY/L3

• Lead Free Status / RoHS Status: Not Compliant

1–2
Features
POS-PHY Level 2 and 3 Compiler User Guide
Table 1–2. Device Family Support
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■
■
■
■
■
■
■
■
■
■
■
Arria
Arria II GX
Cyclone
Cyclone II
Cyclone III
HardCopy
HardCopy III
HardCopy IV E
Stratix
Stratix II
Stratix II GX
Stratix III
Stratix IV
Stratix GX
Other device families
Conforms to POS-PHY level 2 and level 3 specifications
Link-layer or PHY-layer POS-PHY interfaces
Creates bridges between different POS-PHY interfaces
Support for traffic up to a rate of 3.2 gigabits per second (Gbps) (POS-PHY level 3)
or 832 megabits per second (Mbps) (POS-PHY level 2), such as SONET OC-48
Single-PHY (SPHY) or up to 8-channel multi-PHY (MPHY) operation with polled
and direct packet available options
Atlantic
packet MegaCore functions
Selectable POS-PHY interface bus widths (8/16/32 bit) and Atlantic interface bus
widths (8/16/32/64 bit)—allowing translation between different bus types
Parity generation/detection
Configurable first-in first-out (FIFO) options: selectable FIFO width, depth, and fill
thresholds.
Easy-to-use IP Toolbench interface
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
Support for OpenCore Plus evaluation
™
GX
®
®
®
II
™
interface that allows a consistent interface between all Altera cell and
Device Family
Preliminary
Full
Preliminary
Full
Full
Full
Full
Preliminary
Preliminary
Full
Full
Full
Full
Preliminary
Full
No support
© November 2009 Altera Corporation
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