LMK04010BISQE National Semiconductor, LMK04010BISQE Datasheet - Page 45

• Manufacturer Part Number: LMK04010BISQE
• Manufacturer: National Semiconductor

Specifications of LMK04010BISQE

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

C
C
datasheet
C
range, assuming a variable capacitance element is one com-
ponent of the load. F
at the extremes of the circuit’s load capacitance range.
A common range for the pullability ratio, C
The ratio of the load capacitance to the shunt capacitance is
~(n * 1000), n < 10. Hence, picking a crystal with a smaller
Note 47: Performance data and crystal specifications contained in this
section are based on Ecliptek model ECX-6465, 12.288 MHz.
L
0
L1
Integration Bandwidth
= Shunt capacitance of the crystal, specified on the crystal
= Load capacitance
, C
100 Hz – 20 MHz
10 kHz – 20 MHz
L2
100 kHz
10 MHz
100 Hz
10 kHz
= The endpoints of the circuit’s load capacitance
1 MHz
Offset
1 kHz
TABLE 32. Example RMS Jitter and Clock Output Phase Noise for LMK04031 with a
CL1
, F
CL2
12.288 MHz Crystal Driving OSCin (T = 25 °C, V
Clock Output Type
Clock Output Type
= parallel resonant frequencies
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
0
/C
1
, is 250 to 280.
Phase Noise (dBc/Hz)
F
F
CLK
CLK
RMS Jitter (ps)
= 122.88 MHz
= 122.88 MHz
0.279
0.244
0.272
0.251
0.211
0.236
-107
-105
-105
-126
-125
-126
-125
-127
-126
-134
-135
-134
-155
-157
-155
-158
-160
-158
45
PLL2 PDF = 12.288 MHz
PLL2 FPD = 12.288 MHz
(EN_PLL2_REF2X = 0)
(EN_PLL2_REF2X = 0)
The normalized tuning range of the circuit is closely approxi-
mated by:
pullability ratio supports a wider tuning range because this
allows the scale factors related to the load capacitance to
dominate.
Examples of the phase noise and jitter performance of the
LMK04031 with a crystal oscillator are shown in
This table illustrates the clock output phase noise when a
12.288 MHz crystal is paired with PLL1.
CC
F
F
= 3.3 V)
CLK
CLK
= 153.6 MHz
= 153.6 MHz
0.263
0.248
0.269
0.234
0.215
0.235
-106
-103
-104
-124
-124
-123
-124
-125
-124
-133
-133
-132
-154
-155
-153
-158
-159
-158
(Note
47)
PLL2 PDF = 24.576 MHz
PLL2 FPD = 24.576 MHz
(EN_PLL2_REF2X = 1)
(EN_PLL2_REF2X = 1)
F
F
CLK
CLK
30027167
= 122.88 MHz
= 122.88 MHz
0.300
0.218
0.245
0.284
0.193
0.217
-106
-104
-106
-130
-127
-126
-131
-128
-131
-134
-134
-134
-154
-155
-154
-158
-159
-157
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Table
32.