SAE81C91N Infineon Technologies, SAE81C91N Datasheet - Page 16

• Manufacturer Part Number: SAE81C91N
• Manufacturer: Infineon Technologies

Specifications of SAE81C91N

• Number Of Transceivers: 1
• Power Down Mode: Sleep
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Control Register Summary
Register Name
OC
CC
CTRL
MOD
INT
IMSK
BL1
BL2
BRP
RRR1
RRR2
RIMR1
RIMR2
TRSR1
TRSR2
TRRR1
TRRR2
RRPR1
RRPR2
TSCH
TSCL
TCEC
TCD
P0PDR
P1PDR
P0LR
P1LR
P0PR
P1PR
Note:
Semiconductor Group
1)
ro: read only, r/w: read and write access, wo: write only, I: access only with bit IM set.
Address
02
14
12
10
11
0A
00
01
03
04
05
06
07
08
09
18
19
1A
1B
1C
1D
15
16
28
2C
2A
2E
29
2D
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Function
Output-control register
Clock-control register
Control register
Mode/status register
Interrupt register
Interrupt-mask register
Bit-length register 1
Bit-length register 2
Baud-rate prescaler
Receive-ready register 1
Receive-ready register 2
Receive-interrupt-mask register 1
Receive-interrupt-mask register 2
Transmit-request-set register 1
Transmit-request-set register 2
Transmit-request-reset register 1
Transmit-request-reset register 2
Remote-request-pending register 1
Remote-request-pending register 2
Time-Stamp counter high byte
Time-Stamp counter low byte
Transmit-check error counter
Transmit-check data register
Port 0 port-direction register
Port 1 port-direction register
Port 0 latch register
Port 1 latch register
Port 0 pin register
Port 1 pin register
07Feb95@09:05h Intermediate Version
15
SAE 81C90/91
Reset
Value
00
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
XX
00
00
00
00
XX
XX
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Read
Write
r/w, I
wo
r/w
r/w
r/w
r/w
r/w, I
r/w, I
wo, I
r/w
r/w
r/w
r/w
r/w
r/w
wo
wo
ro
ro
r/w
r/w
r/w
ro
r/w
r/w
r/w
r/w
ro
ro
1)