MT41J256M8THR-187E:D Micron Technology Inc, MT41J256M8THR-187E:D Datasheet

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MT41J256M8THR-187E:D

Manufacturer Part Number
MT41J256M8THR-187E:D
Description
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Datasheet

Specifications of MT41J256M8THR-187E:D

Organization
256Mx8
Address Bus
17b
Maximum Clock Rate
1.066GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT41J256M8THR-187E:D
Manufacturer:
MICRON
Quantity:
985
TwinDie
MT41J512M4 – 32 Meg x 4 x 8 Banks x 2 Ranks
MT41J256M8 – 16 Meg x 8 x 8 Banks x 2 Ranks
For component data sheets, refer to Micron’s Web site:
Functionality
The 2Gb (TwinDie™) DDR3 SDRAM uses Micron’s 1Gb
DDR3 die and has similar functionality. This data sheet
provides ball assignments, a general description, func-
tional block diagrams, electrical specifications, and
package dimensions. Refer to Micron’s 1Gb DDR3
SDRAM data sheet for complete specifications. (Speci-
fications for base part number MT41J256M4 correlate
to TwinDie manufacturing part number MT41J512M4;
specifications for base part number MT41J128M8 cor-
relate to TwinDie manufacturing part number
MT41J256M8.)
Features
• Uses 1Gb Micron die
• Two ranks (includes dual CS#, ODT, CKE, and
• Each rank has 8 internal banks
• V
• 1.5V center-terminated push/pull I/O
• JEDEC-standard 78-ball ballout
• Low-profile package (1.35mm MAX thickness)
• T
Table 1:
PDF: 09005aef82fcca5a/Source: 09005aef82ed0bfa
MT41J512M4_32M_16M_twindie.fm - Rev. B 4/09 EN
– 0°C to 85°C: 8192 refresh cycles in 64ms
– 85°C to 95°C: 8192 refresh cycles in 32ms
ZQ balls)
Speed Grade
C
DD
of 0°C to 95°C
= V
-187E
-15E
-187
-25E
-15
-25
DDQ
Key Timing Parameters
Products and specifications discussed herein are subject to change by Micron without notice.
= +1.5V ±0.075V
TM
Data Rate (MT/s)
DDR3 SDRAM
1333
1333
1066
1066
800
800
Target
www.micron.com
10-10-10
1
t
9-9-9
8-8-8
7-7-7
6-6-6
5-5-5
RCD-
Notes: 1. CL = CAS (READ) latency.
Options
• Configuration
• FBGA package (lead-free)
• Timing – cycle time
• Self refresh
• Operating temperature
• Revision
– 32 Meg x 4 x 8 banks x 2 ranks
– 16 Meg x 8 x 8 banks x 2 ranks
– 78-ball FBGA (9mm x 11.5mm)
– 78-ball FBGA (8mm x 11.5mm)
– 1.5ns @ CL = 10 (DDR3-1333)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 8 (DDR3-1066)
– 1.87ns @ CL = 7 (DDR3-1066)
– 2.5ns @ CL = 6 (DDR3-800)
– 2.5ns @ CL = 5 (DDR3-800)
– Standard
– Commercial (0°C ≤ T
t
RP-CL
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2Gb: x4, x8 TwinDie DDR3 SDRAM
t
RCD (ns)
13.5
13.1
12.5
15
15
15
1
C
≤ 95°C)
©2008 Micron Technology, Inc. All rights reserved.
t
RP (ns)
13.5
13.1
12.5
15
15
15
Functionality
Marking
512M4
256M8
-187E
None
None
:D/F
THR
THV
-15E
-187
-25E
CL (ns)
-15
-25
13.5
13.1
12.5
15
15
15

Related parts for MT41J256M8THR-187E:D

MT41J256M8THR-187E:D Summary of contents

Page 1

... MT41J256M8 – 16 Meg Banks x 2 Ranks For component data sheets, refer to Micron’s Web site: Functionality The 2Gb (TwinDie™) DDR3 SDRAM uses Micron’s 1Gb DDR3 die and has similar functionality. This data sheet provides ball assignments, a general description, func- tional block diagrams, electrical specifications, and package dimensions. Refer to Micron’ ...

Page 2

... CS0# BA2 V BA0 A13 V RESET# SS Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 2Gb: x4, x8 TwinDie DDR3 SDRAM Ball Assignments and Descriptions 256 Meg Meg banks x 2 ranks 8K 16K A[13:0] 8 BA[2:0] 1K A[9: NF, NF/TDQS DM, DM/TDQS SSQ DDQ DQ1 DQ3 ...

Page 3

... Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active power-down (row active in any bank) ...

Page 4

... No function: When configured device, these balls are NF. When configured device, these balls are defined as TDQS#, DQ[7:4]. PDF: 09005aef82fcca5a/Source: 09005aef82ed0bfa MT41J512M4_32M_16M_twindie.fm - Rev. B 4/09 EN 2Gb: x4, x8 TwinDie DDR3 SDRAM Ball Assignments and Descriptions REFCA must be maintained at all times (including self REFDQ SSQ Micron Technology, Inc ...

Page 5

... The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. Read and write accesses to the DDR3 SDRAM are burst oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence ...

Page 6

... Figure 3: Functional Block Diagram (16 Meg Banks x 2 Ranks) CS1# RAS# CKE1 CAS# WE# ODT1 ZQ1 PDF: 09005aef82fcca5a/Source: 09005aef82ed0bfa MT41J512M4_32M_16M_twindie.fm - Rev. B 4/09 EN 2Gb: x4, x8 TwinDie DDR3 SDRAM Functional Block Diagrams Rank 1 (32 Meg banks) Rank 0 (32 Meg banks) CK CK# A[13:0], BA[2:0] DQS, DQS# ...

Page 7

... DD greater than 0.6 × MAX operating case temperature. T Figure 4 on page 8). 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T ing operation. Temperature and Thermal Impedance It is imperative that the DDR3 SDRAM device’s temperature specifications, shown in Table 5 on page 8, be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’ ...

Page 8

... Thermal Characteristics Parameter/Condition Operating case temperature Notes: 1. MAX operating case temperature. T (see Figure 4 thermal solution must be designed to ensure the DRAM device does not exceed the max- imum T 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T operation interval refresh rate. The use of self refresh temperature (SRT) or automatic self refresh (ASR), if available, must be enabled ...

Page 9

... DD4R DD2P0 = DD5B DD2P0 = CDD6 DD6 DD6 = DD6ET DD6ET = DD7 DD2P0 = 2 × DD2P0 values reflect the combined current of both individual die 2Gb: x4, x8 TwinDie DDR3 SDRAM Electrical Specifications -25/ -187/ Width -25E -187E 107 117 x4 102 112 x8 127 137 x4/ x4/ All ...

Page 10

... C L 11.50 ±0.10 0.80 TYP 4.50 ±0.05 Micron Technology, Inc., reserves the right to change products or specifications without notice. 10 2Gb: x4, x8 TwinDie DDR3 SDRAM Package Dimensions Solder ball material: 96.5% Sn, 3% Ag, 0.5% Cu Substrate material: Plastic laminate Mold compound: Epoxy novolac Ball A1 ID 1.35 MAX © ...

Page 11

... Ball 11.5 ±0. 0.8 TYP 6.4 CTR Micron Technology, Inc., reserves the right to change products or specifications without notice. 11 2Gb: x4, x8 TwinDie DDR3 SDRAM Package Dimensions Ball A1 ID 1.2 MAX 0.25 MIN ©2008 Micron Technology, Inc. All rights reserved. ...

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