CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet
CYNSE10512A-133FGC
Specifications of CYNSE10512A-133FGC
Related parts for CYNSE10512A-133FGC
CYNSE10512A-133FGC Summary of contents
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... Ayama™ 10000A Network Search Engine Cypress Semiconductor Corporation Document #: 38-02110 Rev. *B CONFIDENTIAL Network Search Engine • 198 Champion Court • San Jose CYNSE10512A CYNSE10256A CYNSE10128A , CA 95134-1709 • 408-943-2600 Revised February 1, 2006 ...
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... Depth Cascading up to Eight Devices in One Block .....................................................................45 5.10.2 Depth Cascading Devices in 4 Blocks .............................................................................47 5.10.3 Depth Cascading for a FULL Signal ..............................................................................................47 5.11 Device Selection in a Cascaded System ................................................................................48 5.12 Power-up Sequence ................................................................................................................49 Document #: 38-02110 Rev. *B CONFIDENTIAL TABLE OF CONTENTS CYNSE10512A CYNSE10256A CYNSE10128A Page 2 of 145 ...
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... AC Test Conditions and Output Loads ..................................................................................134 10.3.1 HSTL I/II ......................................................................................................................................134 10.3.2 LVCMOS 2.5V/1.8V ....................................................................................................................135 11.0 PIN ASSIGNMENT AND PINOUT DIAGRAM ............................................................................136 12.0 ORDERING INFORMATION ......................................................................................................142 13.0 PACKAGE DIAGRAM ................................................................................................................142 Document #: 38-02110 Rev. *B CONFIDENTIAL TABLE OF CONTENTS (continued) CYNSE10512A CYNSE10256A CYNSE10128A Page 3 of 145 ...
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... Figure 6-5. Search Key format on DQ bus for a 288-bit search.............................................................57 Figure 6-6. Timing Diagram for Mixed Single Search (One Device) ......................................................58 Figure 6-7. Multiwidth Configurations Using CYNSE10512A as an Example........................................59 Figure 6-8. Timing Diagram for Mixed MultiSearch (One Device) .........................................................60 Figure 6-9. Multiwidth Configurations Using CYNSE10512A as an Example........................................61 Document #: 38-02110 Rev ...
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... Figure 6-42. Timing Diagram for Mixed Search for the Last Device in Block 3......................................96 Figure 6-43. Hardware Diagram for a Table with Eight Devices for MultiSearch...................................98 Figure 6-44. Multiwidth Configurations Example for MultiSearch with CYNSE10512As .......................99 Figure 6-45. Timing Diagram for Mixed MultiSearch (Eight Devices) for Device 0 ..............................100 Figure 6-46 ...
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... Figure 10-9. Test Condition of 2.5V High-Z LVCMOS I/O Output Load Equivalent.............................135 Figure 10-10. Test Condition of 1.8V High-Z LVCMOS I/O Output Load Equivalent...........................135 Figure 11-1. Pinout Diagram (Top View)..............................................................................................136 Document #: 38-02110 Rev. *B CONFIDENTIAL LIST OF FIGURES (continued) CYNSE10512A CYNSE10256A CYNSE10128A Page 6 of 145 ...
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... Table 6-14. Latency of SADR for different learn widths .......................................................................106 Table 6-14. SRAM Write Cycle Latency from Second Cycle of Learn Instruction ..............................112 Table 6-15. Required Idle Cycles Between Commands .....................................................................125 Document #: 38-02110 Rev. *B CONFIDENTIAL LIST OF TABLES CYNSE10512A CYNSE10256A CYNSE10128A Page 7 of 145 ...
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... Table 10-4. 1.5V AC Table for HSTL Test Condition of Ayama 10000A ............................................134 Table 10-5. 2.5V / 1.8V AC Table for LVCMOS Test Condition of Ayama 10000A ............................136 Table 11-1. Pin Assignment ................................................................................................................138 Table 12-1. Ordering Information ........................................................................................................143 Document #: 38-02110 Rev. *B CONFIDENTIAL CYNSE10512A CYNSE10256A CYNSE10128A Page 8 of 145 ...
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... Features • 512K 36-bit entries in a single device for CYNSE10512A — 256K entries in 72-bit configuration — 128K entries in 144-bit configuration — 64K entries in 288-bit configuration — 32K entries in 576-bit configuration • 256K 36-bit entries in a single device for CYNSE10256A — 128K entries in 72-bit configuration — ...
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... Figure 2-1. Ayama™ 10000A Block Diagram CYNSE10512A CYNSE10256A CYNSE10128A TMS TCK TAP TRST_L Controller TDI TDO SADR[N:0], Pipeline OE_L for and CYNSE10512A, SRAM WE_L 24 for CYNSE10256A, Interface CE_L 23 for Control CYNSE10128A ALE_L MULTI_HIT FULO[1:0]/LHO_1[1:0] LHO[1:0]/LHO_0[1:0] BHO[2:0] Logic SSF ...
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... Fabric Figure 2-2. Example of Switch/Router Implementation Using Ayama 10000A Document #: 38-02110 Rev. *B CONFIDENTIAL Program Memory Ayama 10000A Host Bank ASIC Ayama 10000A Bank Host ASIC SRAM Bank CYNSE10512A CYNSE10256A CYNSE10128A NSE Subsystem SRAM Bank Associative Mode or Index Mode Page 11 of 145 ...
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... The rise time of PARERR_L will depend on the value of the pull-up resistance. Sufficient delay should be allotted for in the error routine after clearing the parity error in the parity control register and before this pin is sampled as part of the next command. Recommended external pull-up resistance range: 4.7K Document #: 38-02110 Rev. *B CONFIDENTIAL Description CYNSE10512A CYNSE10256A CYNSE10128A ), the device uses DDQ_ASIC DDQ_ASIC ...
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... SRAM Address. This bus contains address lines to access off-chip SRAMs that contain V associative data cascaded system of multiple Ayama 10000A NSEs, each corre- DDQ_SRAM sponding SADR bit from all cascaded devices must be tied together for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A. [4] CE_L T, SRAM Chip Enable. This is the chip enable (CE) control for external SRAMs cascaded ...
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... DDQ_JTAG TCK I, Test access port test clock. V DDQ_JTAG TDO T, Test access port test data out. V DDQ_JTAG TMS I, Test access port test mode select. V DDQ_JTAG TRST_L I, Test access port reset. V DDQ_JTAG Document #: 38-02110 Rev. *B CONFIDENTIAL Description CYNSE10512A CYNSE10256A CYNSE10128A Page 14 of 145 ...
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... Data Array, Mask Array and Table Widths The Ayama 10000A device consists of M × 72-bit (M = 256K for CYNSE10512A, 128K for CYNSE10256A, 64K for CYNSE10128A) storage cells referred to as data bits. There is also a mask cell corresponding to each data cell. A database entry includes both the data and mask cells ...
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... Table 4-1. Bit Position Match Global Mask Bit Mask Array Bit Document #: 38-02110 Rev. *B CONFIDENTIAL 72 72 287 143 N 144-bit configuration [5] Data Array Bit CYNSE10512A CYNSE10256A CYNSE10128A 288-bit configuration 262144 for CYNSE10512A 131072 for CYNSE10256A 65536 for CYNSE10128A Search Key Bit Match Result Page 16 of 145 ...
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... Non-Enhanced Mode In the Non-Enhanced mode of operation, the Ayama 10000A device is organized into 32/16/8 partitions (corresponds to CYNSE10512A/256A/128A, respectively) that each can be configured 72 144 288. The 576-bit table width configuration is not supported in this operation mode. The LSB of each 72-bit is designated to indicate whether that entry is used or not ...
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... Mini-Key Register Priority Register Parity Register Block 1 NFA Register Mini-Key Register Priority Register Parity Register Block N NFA Register Mini-Key Register Figure 5-2. Mini-Key Register Contents CYNSE10512A CYNSE10256A CYNSE10128A 127 for CYNSE 10512A 63 for CYNSE10256A 31 for CYNSE10128A 2K 72 Bits 2K Page 18 of 145 ...
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... PARERR_L signal goes Low 4 cycles after the error is detected. Document #: 38-02110 Rev. *B CONFIDENTIAL 512 x 72 Sub-Block 0 Block 0 Sub-Block 1 Block 1 Block 2 Sub-Block 2 Sub-Block 3 Block N CYNSE10512A CYNSE10256A CYNSE10128A 127 for CYNSE 10512A V3 63 for CYNSE10256A 31 for CYNSE10128A th cycle of latency Page 19 of 145 ...
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... PARITY register to obtain the location, reading the BPAR registers to locate blocks that has the error and then fixing those locations. Document #: 38-02110 Rev. *B CONFIDENTIAL cycle cycle cycle cycle incorrect value for PAR[1] T+3 T+4 T+2 T+5 th cycle of latency. For example, with TLSZ = 10 (binary) and CYNSE10512A CYNSE10256A CYNSE10128A cycle cycle cycle cycle T+6 Page 20 of 145 ...
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... MultiSearch When MultiSearch is activated, the Core is divided into two separate arrays. Each array is organized into 64/32/16 blocks (corresponds to CYNSE10512A/CYNSE10256A/CYNSE10128A, respectively 72-bit entries. Each block can be configured width x72, x144, x288, or x576. This separation allows a Search operation to simultaneously perform the search across both arrays ...
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... Leading Search Search GMR Usage CPR Usage Search Size GMR[a], CPR[a] GMR[b], GMR[c], GMR[d] GMR[a], CPR[a] GMR[b] GMR[a] CPR[a] GMR[a] CPR[a] CYNSE10512A CYNSE10256A CYNSE10128A 72-bit Trailing Search Supported Supported Yes Yes Yes Yes Yes Yes No Yes Trailing Trailing Trailing Search Search ...
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... Search Size GMR[a+1] CPR[a+1] GMR[b+1] GMR[c+1] GMR[d+1] GMR[a+1], CPR[a+1] GMR[b+1] GMR[a+1] CPR[a+1] GMR[a+1] CPR[a+1] Array 0 Addresses (hexadecimal) [0:1FFFF] [0:FFFF] [0:7FFF] CYNSE10512A CYNSE10256A CYNSE10128A Trailing Trailing Trailing Search Search GMR Usage CPR Usage 576-bit GMR[a], CPR[a] GMR[b], GMR[c], GMR[d] 288-bit GMR[c], GMR[d] 144-bit ...
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... Search operation does not result in a Search Hit. Refer to Section 5.3 for more information. Document #: 38-02110 Rev. *B CONFIDENTIAL CASCADE Ayama 10000A CASCADE CASCADE Ayama 10000A CASCADE CASCADE Ayama 10000A CASCADE CASCADE Ayama 10000A CASCADE Figure 5-7. Ayama 10000A I/O Interfaces CYNSE10512A CYNSE10256A CYNSE10128A To SRAMs (Associative ASIC (Index) Page 24 of 145 ...
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... Write, next-free address register, partition configuration, hardware and parity control registers. Each of the blocks in the NSE device (128/64/32 2Kx72 blocks in CYNSE10512A/256A/128A respectively) also has one each of Block Mini-Key, Block Priority, Block Parity and Block Next-free Address registers. There are also four Block Priority Register Aliases registers for each Block Priority register that allows an alternative way to update the Block Priority registers ...
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... There is one BNFA per block. See Section 5.4.17. R/W Block Priority Register Aliases. These locations are aliases for the corresponding BPRx. See Section 5.4.18. . Address 72 72 index 143 CYNSE10512A CYNSE10256A CYNSE10128A Description Page 26 of 145 ...
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... Document #: 38-02110 Rev. *B CONFIDENTIAL Even Odd 72 72 GMR 143 Index 100 101 11 102 103 12 104 105 13 106 107 14 108 109 15 110 111 for CYNSE10512A Figure 5-10. Search Successful Register CYNSE10512A CYNSE10256A CYNSE10128A for CYNSE10256A for CYNSE10128A INDEX Page 27 of 145 ...
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... Index. This is the address of the 72-bit entry where a successful search occurs. This index is updated if the device is either a local or global winner in a Search operation for CYNSE10512A, 16 for CYNSE10256A, 15 for CYNSE10128A hit occurs in a 144-bit table, the least-significant bit (LSB) is cleared hit occurs in a 288-bit table, the two LSBs are cleared to 0. ...
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... SADR, CE_L, WE_L, and ALE_L signals. In cycles where none of the Ayama 10000A devices in a cascade drive these signals, this device drives the signals as follows: For CYNSE10512A: SADR = 0x1FFFFFF For CYNSE10256A: SADR = 0xFFFFFF For CYNSE10128A: SADR = 0x7FFFFF ...
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... Address. This field is used to identify the starting address of the data or mask array in a Burst-Read operation. The NSE will automatically increment the value by one after each successive Read of the data or mask array. It must be reinitialized before the next Burst- Read operation for CYNSE10512A, 16 for CYNSE10256A, 15 for CYNSE10128A. [18:M] Reserved for CYNSE10512A, 17 for CYNSE10256A, 16 for CYNSE10128A. ...
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... Write of the data or mask array. It must be reinitialized before the next Burst-Write operation for CYNSE10512A, 16 for CYNSE10256A, 15 for CYNSE10128A. Reserved for CYNSE10512A, 17 for CYNSE10256A, 16 for CYNSE10128A. 0 Length of Burst Access. The device provides the capability to Write from 4 to 511 locations in a single burst ...
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... Figure 5-16. Configuration Register Partition Configuration. In the Non-Enhanced mode, Ayama 10000A is internally divided into 32/16/8 partitions corresponding to CYNSE10512A/256A/128A respectively. Each two bits configures one partition as encoded below: 00: 8K × 72 01: 4K × 144 10: 2K × 288 11: Disabled (does not reduce power consumption in a Search operation) Bit[1:0] configures the first partition, Bit[3:2] configures the second partition and so on ...
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... Refer to IOJTAG above for I/O drive strength encoding. Command and DQ Bus I/Os. The following output signals are part of this group: DQ, ACK, EOT, SSF, SSV, PAR, PARERR_L, MULTI_HIT, and FULL. Refer to IOJTAG above for I/O drive strength encoding. Reserved. Reserved. This field must be set to 0. CYNSE10512A CYNSE10256A CYNSE10128A ...
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... Core. Note that if another Parity operation is performed, this field is updated based upon that operation for CYNSE10512A, 16 for CYNSE10256A (bit [17] is reserved), 15 for CYNSE10128A (bits [17:16] are reserved). Bit[18] is used to indicate whether a mask (=1) or data (=0) entry contained the error. [27:19] Reserved ...
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... Mini-Key. This field contains the Mini-Key to be used for the associated command. 0 Soft Priority Comparison Flag. When set to 1, Search comparison is with entries that has Soft Priority value equal to or higher (lower priority) than PRIORITY. When set to 0, comparison is only with equal value. Reserved. CYNSE10512A CYNSE10256A CYNSE10128A ...
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... Figure 5-21. Search Result Register Index. This field contains the Hit or Miss index inside the Core for CYNSE10512A, 16 for CYNSE10256A, 15 for CYNSE10128A. Reserved for CYNSE10512A, 17 for CYNSE10256A, 16 for CYNSE10128A. Mini-Key. This field contains a copy of the Mini-Key value selected for the Search operation ...
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... Mini-Key in the selected CPR by the command. If there is a match, the associated block is enabled to participate in the operation. Mini-Key #2. See Mini-Key #3 description. Mini-Key #1. See Mini-Key #3 description. Mini-Key #0. See Mini-Key #3 description. Reserved. CYNSE10512A CYNSE10256A CYNSE10128A Description ...
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... CPR selected by the operation matches, the associated sub-block will participate in the operation. If this bit is set to 0, the associated sub-block will not participate in a Search operation. V #2. See V #3 description. V #1. See V #3 description. V #0. See V #3 description. Reserved. CYNSE10512A CYNSE10256A CYNSE10128A PRIORITY1 PRIORITY2 PRIORITY3 23 ...
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... Multi Free Entry in Sub-block #2. See MULTI3 description. F2 [31] 0 Free Entry in Sub-block #2. See F3 description. NFA1 [40:32] 0 Next-free Address for Sub-block #1. See NFA3 description. Document #: 38-02110 Rev. *B CONFIDENTIAL Figure 5-24. Block Parity Register Description NFA1 Figure 5-25. Block NFA Register Description CYNSE10512A CYNSE10256A CYNSE10128A NFA2 NFA3 Page 39 of 145 ...
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... Please see the corresponding BPR fields for the descriptions of the BPRAs fields. Table 5-23 shows the BPRA fields for BPR’s Priority0 Document #: 38-02110 Rev. *B CONFIDENTIAL Description PRIORITY0 Figure 5-26. Block Priority Register Aliases CYNSE10512A CYNSE10256A CYNSE10128A PRIORITY1 PRIORITY2 PRIORITY3 Page 40 of 145 ...
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... HLAT. In the Enhanced mode, the Multi-Hit signal is valid at the same time as SSV. Document #: 38-02110 Rev. *B CONFIDENTIAL Reserved. Priority #0. Reserved. V #0. Reserved. Reserved. Priority #1. Reserved. V #1. Reserved. Reserved. Priority #2. Reserved. V #2. Reserved. Priority #3. Reserved. V #3. Reserved. CYNSE10512A CYNSE10256A CYNSE10128A Description Description Description Description Page 41 of 145 ...
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... Figure 5-29. Ayama 10000A Clocks for All Timing Diagrams Notes: 6. “CLK” internal clock signal. 7. Any reference to “CLK” cycles means one cycle of CLK. Document #: 38-02110 Rev. *B CONFIDENTIAL “Cycle B End” “Cycle B End” Figure 5-28. Ayama 10000A Clocks (CLK1X) CYNSE10512A CYNSE10256A CYNSE10128A Page 42 of 145 ...
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... INDEX field as the address for a Read, Write and Learn operations. Indirect Read operation on the internal registers will return undefined values. Document #: 38-02110 Rev. *B CONFIDENTIAL Total Search CLK1X Cycle Latency Invalid CYNSE10512A CYNSE10256A CYNSE10128A Maximum Operating Speed (CLK1X/CLK2X) 83/166 MHz 100/200 MHz 133/266 MHz Invalid ...
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... When MultiSearch feature is enabled, SADR[M+8] is not used and SADR[M] will indicate Array0 output indicate Array 1 output for CYNSE10512A for CYNSE10256A for CYNSE10128A. 10. Non-Enhanced mode uses NFA register. Enhanced mode uses SRR register. 11. SSR[2:0] is OR-ed with DQ[2:0] to generate the SADR[2:0] values. Document #: 38-02110 Rev. *B ...
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... Document #: 38-02110 Rev. *B CONFIDENTIAL Description Enhanced Mode Non-Enhanced with MSE = 0 1 2-8 9- Yes Yes No Yes Yes Yes Yes No Yes Yes No No Yes CYNSE10512A CYNSE10256A CYNSE10128A CHIPID BLKNUM REGSEL Enhanced Mode with MSE = 1 2-8 9- Yes Yes [12] [12] Yes No Yes No [12] [12] [12 Yes No ...
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... Ayama 10000A #2 LHO[ Ayama 10000A # Ayama 10000A #4 LHO[ LHI LHI Ayama 10000A #5 LHO[ LHI LHI Ayama 10000A #6 LHO[ LHI LHI Ayama 10000A #7 Figure 5-32. Depth Cascading in a Single Block CYNSE10512A CYNSE10256A CYNSE10128A SRAM LHI LHO[ LHI LHO[ LHI LHO[ LHI LHO[ LHI 4 ...
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... BHI[1] Block of 8 Ayama 10000As Block 2 (devices 16–23) BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 Ayama 10000As Block 3 (devices 24–30) BHO[2] BHO[1] Figure 5-33. Depth Cascading 4 Blocks CYNSE10512A CYNSE10256A CYNSE10128A BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] GND BHI[0] BHO[0] BHI[0] BHO[0] ...
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... FULO[ FULI Ayama 10000A FULO[ FULI FULI Ayama 10000A FULO[ FULI FULI Ayama 10000A FULO[ FULI FULI Ayama 10000A FULO[1] FULO[0] CYNSE10512A CYNSE10256A CYNSE10128A VDDQ FULO[0] FULL VDDQ FULO[0] FULL VDDQ FULO[0] FULL VDDQ FULL VDDQ FULL VDDQ FULL VDDQ FULL ...
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... RSTL VDD VDDQ CLK2X PHS_L TRST_L asynchronous delay TRST_L PLL lock time, 0.5 ms Figure 5-35. Proper Power-up Sequence CYNSE10512A CYNSE10256A CYNSE10128A ) level reaches 90% point. DD when V is stable. TRST_L can be tied to DDQ DD Device ready for functional accesses t ...
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... Extended Address (EADR) The EADR field of the CMD bus, CMD[8:6], allows flexibility in the accessing of associated data SRAM. For all operations, the EADR field is mapped to the most significant bits of the SADR output bus. SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, and SADR[23:21] for CYNSE10128A. ...
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... EADR[1:0] 0 [13] 0 EADR[1:0] 0 0=Single-Search [13] EADR[1:0] 1=Multi-Search SSR[2:0] [13] 0 EADR[1:0] 00: x72; 01: x144; 1X:x288/x576 0 (all except last cycle); 0X:x288/x576 (last cycle) CYNSE10512A CYNSE10256A CYNSE10128A Single Burst 0 = Single GMR[2: Burst 0=x72 or x144 GMR[2:0] 1=x288 (f irst cycle) 0=x288 (last cycle) CMPR[3:0] CMPR[3: Single ...
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... The host ASIC selects the Ayama 10000A device for which ID[4:0] matches the DQ[25:21] lines. If DQ[25:21] = 11111, the host ASIC selects the Ayama 10000A with the LDEV bit set. The host ASIC also supplies SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for CYNSE10128A on CMD[8:6] in cycle A of the Read instruction if the Read is directed to the external SRAM. ...
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... Note that when Parity feature is enabled masks will be ignored and all bits will be written as presented in the DQ bus. Write is a blocking operation and must be completed before the next operation can be issued. Document #: 38-02110 Rev. *B CONFIDENTIAL cycle cycle cycle cycle cycle cycle cycle cycle Read Data0 0 Data1 CYNSE10512A CYNSE10256A CYNSE10128A cycle cycle cycle cycle Data3 0 Data2 0 Page 53 of 145 ...
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... DQ bus. The host ASIC also supplies the GMR index to mask the Write to the data or mask array location on {CMD[10], CMD[5:3]}. For SRAM WRITEs, the host ASIC must supply the SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for CYNSE10128A on CMD[8:6]. The host ASIC sets CMD[ for a normal Write. ...
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... Mini-Key(s) selected by the GMR field. For Ayama 10512, this corresponds to 128 parallel locations (128 blocks, 1 location per block). Document #: 38-02110 Rev. *B CONFIDENTIAL cycle cycle cycle cycle Write A B Data0 Data1 Data2 CYNSE10512A CYNSE10256A CYNSE10128A cycle cycle should be driven to zero in this cycle Data3 0 Page 55 of 145 ...
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... N = 256k for CYNSE10512A, 128k for CYNSE10256A, 64k for CYNSE10128A N/2 x 144 N/4 x 288 N/8 x 576 N = 2048k for CYNSE10512A, 1024k for CYNSE10256A, 512k for CYNSE10128A N/2 x 144 N/4 x 288 N/8 x 576 N = 7936k for CYNSE10512A, 3968k for CYNSE10256A, 1984k for CYNSE10128A Reserved Page 56 of 145 ...
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... Notice: Data on DQ bus during 1 [143:72] 0x2 is compared to lowest address 72-bit word of the 288-bit entry; Data on DQ bus during 2 [71:0] 0x3 is compared to 2 word of the 288-bit entry so on and so : forth... : CYNSE10512A CYNSE10256A CYNSE10128A NSE organization [71:0] [71:0] [143:72] [215:144] [287:216] 0x0 ...
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... GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same bits that will be driven on SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for CYNSE10128A if it has a hit. If Enhanced Mode and MultiSearch Enable bits are both set to 1in the Command Resister, CMD[8] has to be set to 0 for Single Searches. For 288-bit and 576-bit Single Searches, all Cycle A CMD[8] bits have to be set to 0’ ...
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... Figure 6-7. Multiwidth Configurations Using CYNSE10512A as an Example Referring to Figure 6-7, if the CYNSE10512A device is used in the Non-Enhanced Mode, the CFG field in the Configuration Register should be configured to “AAAA555500000000” (hex) in order to have three individual tables within a device. If the device is used in the Enhanced Mode, the NES field in the Block Mini-Key Register (BMR) should be configured as follows: • ...
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... GMR pair for use in this Search operation. CMD[7:6] signals must be driven with the same bits that will be driven on SADR[24:23] for CYNSE10512A, SADR[23:22] for CYNSE10256A, SADR[22:21] for CYNSE10128A by this device if it has a hit. CMD[8] must be driven high on all Cycle A’ command for MultiSearch operation. Note, CMD[8] must be driven low for all Cycle A’ ...
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... La and Lb, will be driven as part of the SRAM address on the SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on page 113 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A. 6. Reading CMPR registers after Multisearches: You can only do this if your leading and trailing searches are of same width. ...
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... LHI Ayama 10000A #3 LHO[ Ayama 10000A #4 LHI LHO[ LHI LHI Ayama 10000A #5 LHO[ LHI LHI Ayama 10000A #6 LHO[ LHI LHI Ayama 10000A #7 CYNSE10512A CYNSE10256A CYNSE10128A SRAM LHO[ LHO[ LHO[ BHO[0] BHO[0] BHO[1] BHO[1] BHO[2] BHO[2] LHO[1] LHO[0] Page 62 of 145 ...
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... SSV z SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A CFG[N:0] are all zeroes for Non-Enhanced Mode for CYNSE10512A, 31 for CYNSE10256A, 15 for CYNSE10128A NES = 00 (binary) in each block for Enhanced Mode. HLAT = 010 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0]. ...
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... SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A CFG[N:0] are all zeroes for Non-Enhanced Mode for CYNSE10512A, 31 for CYNSE10256A, 15 for CYNSE10128A. NES = 00 (binary) in each block for Enhanced Mode. HLAT = 010 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0]. ...
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... GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same bits that will be driven on SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for CYNSE10128A by this device if it has a hit. If Enhanced Mode and MultiSearch Enable bits are both set to 1in the Command Resister, CMD[8] has to be set to 0 for Single Searches. For 288-bit and 576-bit Single Searches, all Cycle A CMD[8] bits have to be set to 0’ ...
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... Mini-Key scheme (for Enhanced Mode) will be the winning entry, and its location address L will be driven as part of the SRAM address on the SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on page 113 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A. The global winning device will drive the bus in a specific cycle global miss cycle, the device with LRAM = 1 (default driving device for the SRAM bus) and LDEV = 1 (default driving device for SSF and SSV signals) will be the default driver for such missed cycles ...
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... Thirty-first device (device 30): TLSZ = 10 (binary), HLAT = 001 (binary), LRAM = 1 (binary), and LDEV = 1 (binary). • For Non-Enhanced Mode, CFG[63:0] = 5555555555555555 (hex) for all devices for CYNSE10512A. CFG[31:0] = 55555555 (hex) for all devices for CYNSE10256A, and CFG[15:0] = 5555 (hex) for all devices for CYNSE10128A. For Enhanced Mode, NES in each block for all devices should be set to “ ...
Page 68
... BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 Ayama 10000As Block 2 (Devices 16–23) BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 Ayama 10000As Block 3 (Devices 24–30) BHO[2] BHO[1] CYNSE10512A CYNSE10256A CYNSE10128A SRAM BHI[0] GND BHO[0] BHI[0] GND BHO[0] BHI[0] GND BHO[0] BHI[0] BHO[0] ...
Page 69
... SSV z SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 70
... SSV z SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 71
... SSV z SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0] stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI(6:0) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 72
... SSV z SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 73
... SSV z SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 74
... SSV z SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 75
... SSV z SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 76
... SSV z SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 77
... SSV z SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A HLAT = 001 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]. ...
Page 78
... GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same bits that will be driven on SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for CYNSE10128A by this device if it has a hit. CMD[9] must be driven to logic high to indicate a 144-bit search ...
Page 79
... L will be driven as part of the SRAM address on the SADR[N:0] lines (see “SRAM PIO Access” on page 113 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A. The global winning device will drive the bus in a specific cycle. On global miss cycles, the device with LRAM = 1 (binary) and LDEV = 1 (binary) will be the default driver for such missed cycles ...
Page 80
... Figure 6-29 shows the same for device number 1 and number 7 (the last device in this specific table) respectively. Table 6-11. Hit/Miss Assumptions Search Number Device 0 Device 1 Devices 2–6 Device 7 Document #: 38-02110 Rev. *B CONFIDENTIAL 1 Hit Miss Miss Miss Miss Miss Miss CYNSE10512A CYNSE10256A CYNSE10128A 2 3 Miss Hit Miss Miss Miss Page 80 of 145 ...
Page 81
... SSV z SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0]. Note: Each bit in LHO[1:0] is the same logical signal. Figure 6-27. Timing Diagram for 576-bit Single Search Device Number 0 Document #: 38-02110 Rev ...
Page 82
... SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0]. Note: Each bit in LHO[1:0] is the same logical signal. Figure 6-28. Timing Diagram for 576-bit Single Search Device Number 1 Document #: 38-02110 Rev ...
Page 83
... SSV 0 SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 1 (binary), LDEV = 1 (binary). Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0]. Note: Each bit in LHO[1:0] is the same logical signal. Figure 6-29. Timing Diagram for 576-bit Single Search Device Number 7 (Last Device) Document #: 38-02110 Rev ...
Page 84
... L will be driven as part of the SRAM address on the SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on page 113 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A. The global winning device will drive the bus in a specific cycle global miss cycle, the device with LRAM = 1 (binary) (default driving device for the SRAM bus) and LDEV = 1 (binary) (default driving device for SSF and SSV signals) will be the default driver for such missed cycles ...
Page 85
... Command register all zeroes for Non-Enhanced Mode, NES = “00” (binary) for all blocks for Enhanced Mode), devices containing x144 tables (CFG[63:0] field in Command register for CYNSE10512A = 5555555555555555 (hex), CFG[31:0] = 55555555 (hex) for CYNSE10256A, CFG[15:0] = 5555 (hex) for CYNSE10128A for Non-Enhanced Mode, NES = “ ...
Page 86
... WE_L OE_L SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A For Non-Enhanced Mode, CFG = all zeroes NES = 00 (binary) in all blocks for Enhanced Mode, x72 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Figure 6-32. Timing Diagram for Mixed Search for Devices Above Block 0 Winning Device Document #: 38-02110 Rev ...
Page 87
... WE_L OE_L SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A CFG = all zeroes for Non-Enhanced Mode NES = 00 (binary) in all blocks for Enhanced Mode, x72 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Figure 6-33. Timing Diagram for Mixed Search for Block 0 Winning Device Document #: 38-02110 Rev ...
Page 88
... WE_L OE_L SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A CFG = all zeroes for Non-Enhanced Mode NES = 00 (binary) in all blocks for Enhanced Mode, x72 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0, LDEV = 0 (binary). Figure 6-34. Timing Diagram for Mixed Search for Devices Below Block 0 Winning Device Document #: 38-02110 Rev ...
Page 89
... CE_L ALE_L WE_L OE_L SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A For Non-Enhanced Mode: CYNSE10512A: CFG[63:0] = 5555555555555555h; CYNSE10256A: CFG[31:0] = 55555555h; CYNSE10128A: CFG[15:0] = 5555h. NES = 01 (binary) in all blocks for Enhanced Mode, x144 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). ...
Page 90
... CE_L ALE_L WE_L OE_L SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A For Non-Enhanced Mode: CYNSE10512A: CFG[63:0] = 5555555555555555h; CYNSE10256A: CFG[31:0] = 55555555h; CYNSE10128A, CFG[15:0] = 5555h. NES = 01 (binary) in all blocks for Enhanced Mode, x144 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). ...
Page 91
... CE_L ALE_L WE_L OE_L SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A For Non-Enhanced Mode: CYNSE10512A: CFG[63:0] = 5555555555555555h; CYNSE10256A: CFG[31:0] = 55555555h; CYNSE10128A, CFG[15:0] = 5555h. NES = 01 (binary) in all blocks for Enhanced Mode, x144 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). ...
Page 92
... CE_L ALE_L WE_L OE_L SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A For Non-Enhanced Mode: CYNSE10512A: CFG[63:0] = AAAAAAAAAAAAAAAAh; CYNSE10256A: CFG[31:0] = AAAAAAAAh; CYNSE10128A, CFG[15:0] = AAAAh. NES = 10 (binary) in all blocks for Enhanced Mode, x288 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). ...
Page 93
... SADR[M:0] CE_L ALE_L WE_L OE_L SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A For Non-Enhanced Mode: CYNSE10512A: CFG[63:0] = AAAAAAAAAAAAAAAAh; CYNSE10256A: CFG[31:0] = AAAAAAAAh; CYNSE10128A, CFG[15:0] = AAAAh. NES = 10 (binary) in all blocks for Enhanced Mode, x288 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary) ...
Page 94
... CE_L ALE_L WE_L OE_L SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A For Non-Enhanced Mode: CYNSE10512A: CFG[63:0] = AAAAAAAAAAAAAAAAh; CYNSE10256A: CFG[31:0] = AAAAAAAAh; CYNSE10128A, CFG[15:0] = AAAAh. NES = 10 (binary) in all blocks for Enhanced Mode, x288 search. HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). ...
Page 95
... CE_L ALE_L WE_L OE_L SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A For Non-Enhanced Mode: CYNSE10512A: CFG[63:0] = AAAAAAAAAAAAAAAAh; CYNSE10256A: CFG[31:0] = AAAAAAAAh; CYNSE10128A, CFG[15:0] = AAAAh. NES = 10 (binary) in all blocks for Enhanced Mode, x288 search. HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary). ...
Page 96
... ALE_L WE_L 1 OE_L SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A For Non-Enhanced Mode: CYNSE10512A: CFG[63:0] = AAAAAAAAAAAAAAAAh; CYNSE10256A: CFG[31:0] = AAAAAAAAh; CYNSE10128A, CFG[15:0] = AAAAh. NES = 10 (binary) in all blocks for Enhanced Mode, x288 search HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 1 (binary), LDEV = 1 (binary). ...
Page 97
... L will be driven as part of the SRAM address on the SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on page 113 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A. Note. The Learn command is supported for only one of the blocks consisting eight devices in a depth-cascaded table of more than one block ...
Page 98
... LHI_1_L LHO_1_L[1] LHO_1_L[ LHI_1_L LHO_1_L[1] LHO_1_L[ LHI_1_L LHO_1_L[1] LHO_1_L[ LHI_1_L LHO_1_L[0] V DDQ_ASIC LHI_1_L LHO_1_L[0] V DDQ_ASIC LHI_1_L LHO_1_L[ LHI_1_L LHO_1_L[1] LHO_1_L[0] LHO_0[1] LHO_0[0] CYNSE10512A CYNSE10256A CYNSE10128A V DDQ_ASIC LHI_0 LHO_0[1] LHO_0[0] V DDQ_ASIC LHI_0 LHO_0[1] LHO_0[0] V DDQ_ASIC LHI_0 LHO_0[1] LHO_0[0] V DDQ_ASIC LHI_0 LHO_0[1] LHO[0] V ...
Page 99
... Devices 0 and 1, 256K total entries in each array Devices 2 and 3, 128K total entries in each array Devices 128K total entries in each array Figure 6-44. Multiwidth Configurations Example for MultiSearch with CYNSE10512As • The timing diagrams below correspond to the Hit/Miss assumptions defined in Table 6-13. Table 6-13. Hit/Miss Assumptions in MultiSearchMode Search Number #1 (x72– ...
Page 100
... WE_L OE_L SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A NES = 00 (binary) in all blocks for Enhanced Mode, x72 search. HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Figure 6-45. Timing Diagram for Mixed MultiSearch (Eight Devices) for Device 0 Document #: 38-02110 Rev. *B ...
Page 101
... WE_L OE_L SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A NES = 00 (binary) in all blocks for Enhanced Mode, x72 search. HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Figure 6-46. Timing Diagram for Mixed MultiSearch (Eight Devices) for Device 1 Document #: 38-02110 Rev. *B ...
Page 102
... WE_L OE_L SSV SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A NES = 01 (binary) in all blocks for Enhanced Mode, x144 search. HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Figure 6-47. Timing Diagram for Mixed MultiSearch (Eight Devices) for Device 2 Document #: 38-02110 Rev. *B ...
Page 103
... OE_L SSV 0 SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A NES =10 (binary) in all blocks for Enhanced Mode, x288 search HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary). Figure 6-48. Timing Diagram for Mixed MultiSearch (Eight Devices) for Device 7 Document #: 38-02110 Rev. *B ...
Page 104
... GMR pair for use in this Search operation. CMD[7:6] signals must be driven with the same bits that will be driven on SADR[24:23] for CYNSE10512A, SADR[23:22] for CYNSE10256A, SADR[22:21] for CYNSE10128A by this device if it has a hit. CMD[8] must be set high for MultiSearch operation. Note, CMD[8] must be driven low for all Cycle A’ ...
Page 105
... The SRR register is updated after a Search operation. Only the LSB of each entry is used, regardless of width, to indicate whether that entry is free (=0 (binary)) or not (=1 (binary)). Document #: 38-02110 Rev. *B CONFIDENTIAL Latency of SADR field in CLK1X cycles x72 x144 x288 x576 CYNSE10512A CYNSE10256A CYNSE10128A 5+TLSZ 5+TLSZ 4+TLSZ 2+TLSZ Page 105 of 145 ...
Page 106
... Figure 6-49. Timing Diagram of 72-bit Learn from DQ Bus and CMPR Registers (One Device) Document #: 38-02110 Rev. *B CONFIDENTIAL cycle cycle cycle cycle cycle cycle Learn Learn Learn Mask Learn from CMPR CMPR CMPR a b x72 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A CYNSE10512A CYNSE10256A CYNSE10128A cycle cycle cycle cycle ...
Page 107
... Figure 6-50. Timing Diagram of 288-bit Learn from DQ Bus and CMPR Registers (One Device) Document #: 38-02110 Rev. *B CONFIDENTIAL cycle cycle cycle cycle cycle cycle 288-bit Learn 288-bit Learn Learn Mask Learn from CMPR CMPR CMPR CMPR CMPR for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A CYNSE10512A CYNSE10256A CYNSE10128A cycle cycle cycle cycle Page 107 of 145 ...
Page 108
... Figure 6-51. Timing Diagram of 576-bit Learn from DQ Bus (One Device) Document #: 38-02110 Rev. *B CONFIDENTIAL cycle cycle cycle cycle cycle cycle 576-bit Learn CMPR CMPR CMPR CMPR for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A CYNSE10512A CYNSE10256A CYNSE10128A cycle cycle cycle cycle Page 108 of 145 ...
Page 109
... The Ayama 10000A device updates the signal after each Write or Learn command to a data array. Document #: 38-02110 Rev. *B CONFIDENTIAL cycle cycle cycle cycle cycle cycle 576-bit Learn CMPR CMPR CMPR CMPR for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A CYNSE10512A CYNSE10256A CYNSE10128A cycle cycle cycle cycle Page 109 of 145 ...
Page 110
... TLSZ = 01 (binary), LRAM = 1 (binary), LDEV = 1 (binary). Document #: 38-02110 Rev. *B CONFIDENTIAL cycle cycle cycle cycle cycle cycle Learn2 Learn1 X Comp2 Comp1 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A Figure 6-53. Timing Diagram of Learn CYNSE10512A CYNSE10256A CYNSE10128A cycle cycle cycle cycle cycle cycle Page 110 of 145 ...
Page 111
... Figure 6-54. Timing Diagram of Learn (Except on the Last Device [TLSZ = 01 (binary)]) Document #: 38-02110 Rev. *B CONFIDENTIAL cycle cycle cycle cycle cycle cycle Learn2 Learn1 X Comp2 Comp1 X X 1A1B for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A CYNSE10512A CYNSE10256A CYNSE10128A cycle cycle cycle cycle Page 111 of 145 ...
Page 112
... For a Learn in a 72-bit-configured table, the even-numbered comparand specified by this index will be written. CMD[8:6] carries the bits that will be driven on SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for CYNSE10128A in the SRAM Write cycle. ...
Page 113
... Cycle 4: The host ASIC keeps DQ[71: three-state condition. • Cycle 5: The selected device starts to drive DQ[71:0] and drives ACK from High-Z to LOW. • Cycle 6: The selected device drives the Read address on SADR[N:0] lines ( for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A) and drives ACK HIGH, CE_L LOW, and ALE_L LOW. ...
Page 114
... Cycle 5: The selected device continues to drive DQ[71:0] and drives ACK from High-Z to LOW. • Cycle 6: The selected device drives the Read address on SADR[N:0] lines ( for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A) and drives ACK HIGH, CE_L LOW, WE_L HIGH, and ALE_L LOW. ...
Page 115
... Ayama 10000A # Ayama 10000A #4 LHO[ LHI LHI Ayama 10000A #5 LHO[ LHI LHI Ayama 10000A #6 LHO[ LHI LHI Ayama 10000A #7 CYNSE10512A CYNSE10256A CYNSE10128A SRAM LHI LHO[ LHI LHO[ LHI LHO[ LHI LHO[ LHI BHO[0] BHO[0] BHO[1] BHO[1] BHO[2] BHO[2] LHO[1] LHO[0] ...
Page 116
... TLSZ = 01 , HLAT = 000 (binary) Figure 6-58. SRAM Read of Device # Block of Eight Devices Document #: 38-02110 Rev. *B CONFIDENTIAL cycle cycle cycle cycle Read B z Address , LRAM = 0 , LDEV = 0 (binary) (binary) CYNSE10512A CYNSE10256A CYNSE10128A cycle cycle Address driven by selected Ayama 10000A (binary) Page 116 of 145 ...
Page 117
... Cycle 1A: The host ASIC applies the Read instruction to CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. During this cycle, the host ASIC also supplies SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for CYNSE10128A on CMD[8:6]. ...
Page 118
... ALE_L z SADR[M:0] z ACK z SSV z SSF for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A TLSZ = 10 (binary), HLAT = 010 (binary), LRAM = 0 (binary), LDEV = 0 (binary) Figure 6-61. SRAM Read of Device # Bank of 31 Devices Document #: 38-02110 Rev. *B CONFIDENTIAL BHI[2] BHI[1] Block of 8 Ayama 10000As Block 0 (devices 0–7) ...
Page 119
... Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address with DQ[20:19] set select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also supplies SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for CYNSE10128A on CMD[8:6] in this cycle. ...
Page 120
... WE_L 1 CE_L 1 ALE_L z SADR z ACK SSV 0 0 SSF TLSZ = 00 (binary), HLAT = 000 (binary), LRAM = 1 (binary), LDEV = 1 (binary) Document #: 38-02110 Rev. *B CONFIDENTIAL cycle cycle cycle cycle Write Address Figure 6-63. SRAM Write Access CYNSE10512A CYNSE10256A CYNSE10128A cycle cycle Address Page 120 of 145 ...
Page 121
... Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address with DQ[20:19] set select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also supplies SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for CYNSE10128A on CMD[8:6] in this cycle. ...
Page 122
... OE_L WE_L z CE_L z ALE_L z SADR[M: ACK z SSV z SSF TLSZ = 01 (binary), HLAT = XXX, LRAM = 0 (binary), LDEV = 0 (binary for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A Figure 6-65. SRAM Write of Device # Block of Eight Devices Document #: 38-02110 Rev. *B CONFIDENTIAL cycle cycle cycle cycle cycle cycle Write ...
Page 123
... Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address with DQ[20:19] set select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also supplies SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for CYNSE10128A on CMD[8:6] in this cycle. ...
Page 124
... SADR[M:0] z ACK z SSV z SSF TLSZ = 10 (binary), HLAT = XXX, LRAM = 0 (binary), LDEV = 0 (binary for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A Figure 6-68. SRAM Write of Device #0 in Bank of 31 Devices Document #: 38-02110 Rev. *B CONFIDENTIAL BHI[2] BHI[1] Block of 8 Ayama 10000As Block 0 (devices 0–7) BHO[2] ...
Page 125
... SSV 0 SSF TLSZ = 10 (binary), HLAT = XXX, LRAM = 1 (binary), LDEV = 1 (binary for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A Figure 6-69. SRAM Write Through Device #30 in Bank of 31 Devices 6.8 Timing Sequences for Back-to-Back Operations Table 6-16 shows the idle cycle requirements between operations. The operations in the second column represent operations already performed, and the operations in the first row are those we would like to perform next ...
Page 126
... Search1 Search3 Search5 x72 x72 x144 x72 x144 Search2 Search4 Searches 1 and 2 shows Search 3 shows x144 x72 table full table not full CYNSE10512A CYNSE10256A CYNSE10128A cycle cycle cycle cycle cycle M-Search3 tables 1 M-Search2 Array 0 table is not full, Array 1 is full cycle ...
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... Part Number. This is the part number for CYNSE10128A. This is the part number for CYNSE10256A. This is the part number for CYNSE10512A. Manufacturer ID. This field is the same as the manufacturer ID used in the TAP controller. ...
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... Document #: 38-02110 Rev. *B CONFIDENTIAL 80% Search Load 40% Search Load 80 100 Operating Frequency (Mhz) 66 MHz 83 MHz 10.18 12.41 10.25 12.48 6.79 8.17 8.97 10.86 CYNSE10512A CYNSE10256A CYNSE10128A 120 100 MHz 116 MHz 133 MHz 14.61 16.62 18.74 14.67 16.69 18.79 9.52 10.77 12.07 12.72 14 ...
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... The operating current for NSE devices is highly application dependent, and can vary widely due to a number of system configurations. Please contact Cypress and provide system characteristics to receive application specific values. Description Description 30 pF, and all others 6 pF REF CYNSE10512A CYNSE10256A CYNSE10128A 2.5V ...
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... Based load of 30 pF. This parameter is guaranteed by design and is not production tested. Document #: 38-02110 Rev. *B CONFIDENTIAL Description [26] [26] [26] [26] [26] [27, 29] [27, 29] [27, 28] [30] [30] [30] [26] [26, 30] [26] [26, 30] [26, 30] CYNSE10512A CYNSE10256A CYNSE10128A Ayama Ayama Ayama 10000A-083 10000A-100 10000A-133 Min. Max. Min. Max. Min. Max. 100 166 100 200 100 266 0 ...
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... Document #: 38-02110 Rev. *B CONFIDENTIAL Figure 10-1. AC Timing Waveforms with CLK2X CYNSE10512A CYNSE10256A CYNSE10128A Page 131 of 145 ...
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... CYNSE10512A CYNSE10256A CYNSE10128A Ayama 10000A- Ayama 10000A- 100 133 Min. Max. Min. Max. Unit 50 100 50 133 MHz 0.5 0.5 ms 4.5 3.4 ns 4.5 3 ...
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... TDIH t TCK Clock LOW to TDO Valid TDOV t TCK Clock LOW to TDO Invalid TDOX Document #: 38-02110 Rev. *B CONFIDENTIAL Ayama 10000A- 083 Min. Max. 10 100 CYNSE10512A CYNSE10256A CYNSE10128A Ayama 10000A- Ayama 10000A- 100 133 Min. Max. Min. Max. Unit 10 10 MHz 100 100 ...
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... T im ing G roup ing G roup I_H ing G roup [0:10 ing G roup ing G roup LI ing G roup 6 ing G roup ing G roup Figure 10-2. AC Timing Waveforms with CLK1X Document #: 38-02110 Rev. *B CONFIDENTIAL _FU _FN CYNSE10512A CYNSE10256A CYNSE10128A _FU _FU Page 134 of 145 ...
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... Figure 10-3. HSTL I/II I/O Input Waveform 50Ω 1 OUT 25Ω 1 OUT 1.5V DDQ 479Ω D For high-Z OUT 6 pF 523Ω CYNSE10512A CYNSE10256A CYNSE10128A Results 0.25 to 1.25V Faster than 1 V/ns (see Figure 10-3) 0.75V 0.75V DDQ DDQ Page 135 of 145 ...
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... OUT 2.5V DDQ 479Ω D OUT 6 pF Ω 523 V = 1.8V DDQ 470Ω D OUT 6 pF 470Ω CYNSE10512A CYNSE10256A CYNSE10128A Results GND to 2.5V/1.8V < 1.2 ns (see Figure 10-7) < 1.2 ns (see Figure 10-7) 1.25V/0.9V 1.25V/0.9V DDQ For high-Z For high-Z Page 136 of 145 ...
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... DD_P DR DR DDQ_S CLK _M ODE DDQ_S DDQ_S CLK DR DDQ_S Figure 11-1. Pinout Diagram (Top View) CYNSE10512A CYNSE10256A CYNSE10128A LHI [ 2 ] LHI [ LHI [ 3 ] LHI [ DDQ_J DQ DDQ_A RR_L DQ DDQ_A DDQ_A DQ DQ DDQ_A ...
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... AC3 GND AE10 GND AE11 GND AE12 GND AE13 GND AE14 GND AE15 INPUT AE16 I/O AE17 1.2V AE18 1.2V AE19 1.2V AE2 CYNSE10512A CYNSE10256A CYNSE10128A Signal Name Signal Type CMD[2] INPUT V 1. GND SS FULL OUTPUT-T ACK OUTPUT-T V GND SS V 1.2V DD ...
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... OUTPUT-T B7 INPUT B8 INPUT B9 I/O C1 I/O C10 I/O C11 1.5V/1.8V/2.5V C12 I/O C13 I/O C14 I/O C15 INPUT C16 I/O C17 CYNSE10512A CYNSE10256A CYNSE10128A Signal Name Signal Type DQ[10] I/O DQ[06] I/O V 1.5V/1.8V/2.5V DDQ_ASIC DQ[00] I/O V 1.5V/1.8V/2.5V DDQ_ASIC V GND CONNECT DQ[70] I ...
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... GND G1 GND G2 OUTPUT-T G23 GND G24 INPUT G25 GND G26 GND G3 1.2V G4 OUTPUT-T H1 OUTPUT-T H2 1.2V H23 GND H24 GND H25 GND H26 GND H3 CYNSE10512A CYNSE10256A CYNSE10128A Signal Name Signal Type DQ[13] I/O PAR[1] I/O [32] TMS INPUT 1.2V DD SADR[1] OUTPUT ...
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... P14 1.5V/1.8V/2.5V P15 GND P16 GND P2 GND P23 GND P24 GND P25 GND P26 1.2V U24 1.2V U25 1.5V/1.8V/2.5V U26 GND U3 GND U4 CYNSE10512A CYNSE10256A CYNSE10128A Signal Name Signal Type V GND SS LHI[2] INPUT LHI[3] INPUT V GND SS SADR[11] OUTPUT-T BHI[0] INPUT ...
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... W26 GND W3 GND W4 GND Y1 GND Y2 GND Y23 1.2V Y24 1.2V Y25 INPUT Y26 OUTPUT-T Y3 1.2V Y4 1.2V INPUT 1.5V/1.8V/2.5V GND CYNSE10512A CYNSE10256A CYNSE10128A Signal Name Signal Type FULI[2] INPUT FULI[3] INPUT V GND SS CE_L OUTPUT-T V 1.5V/1.8V/2.5V DDQ_SRAM WE_L OUTPUT-T FULI[4] INPUT V GND SS V 1.5V/1.8V/2.5V ...
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... HFC-BGA FG388A 3.32 MAX 0.15(4X) CYNSE10512A CYNSE10256A CYNSE10128A Max. Freq. Temp. Range 83 MHz Comm 100 MHz Comm 133 MHz Comm 83 MHz Comm 100 MHz Comm 133 MHz Comm 83 MHz Comm 100 MHz ...
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... Document History Page Document Title: CYNSE10512A/CYNSE10256A/CYNSE10128A Ayama 10000A Network Search Engine Document Number: 38-02110 ECN Issue Orig. of REV. NO. Date Change ** 295472 See ECN CNG *A 393322 See ECN KMQ CNG Document #: 38-02110 Rev. *B CONFIDENTIAL Description of Change New data sheet based on 38-02-069 with the following changes: ...
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... Document History Page (continued) Document Title: CYNSE10512A/CYNSE10256A/CYNSE10128A Ayama 10000A Network Search Engine Document Number: 38-02110 ECN Issue Orig. of REV. NO. Date Change *A 393322 See ECN KMQ CNG *B 421311 See ECN VSP/ TNT Document #: 38-02110 Rev. *B CONFIDENTIAL Description of Change Included PARERR_L into signal groupings with DQ in Figures 10-1 and 10-2. ...