CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 10

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
2.0
Cypress Semiconductor Corporation’s (Cypress’s) Ayama™ 10000A Network Search Engine (NSE) is designed to be a high-
performance, pipelined, synchronous, 512K/256K/128K 36-bit entries NSE. This high-speed, high-capacity Ayama 10000A NSE
can be deployed in a variety of networking and communications applications. It can be used to accelerate network protocols such
as Longest-Prefix Match (CIDR), ARP, MPLS, and other layer 2, 3, and 4 protocols. The performance and features of the
Ayama 10000A make it attractive in applications such as Enterprise LAN switches and routers, and broadband switching and/or
routing equipment that supports multiple data rates at OC–48 and beyond. Ayama 10000A can operate at a maximum perfor-
mance of 266 million searches per second (MSPS).
The Ayama 10000A is designed to be scalable in order to support network database sizes of up to 15872K 36-bit entries
specifically for environments that require large network policy databases. It includes features that ease table management, reduce
power consumption and improve data integrity. The device can have its features individually enabled or disabled for flexibility
based on the needs of the applications. The Ayama 10000A’s Data and Mask arrays that make up the Core are organized into
blocks that can be individually configured to optimize the device performance and provide even more flexibility.
Figure 2-1 below shows the block diagram of the Ayama 10000A. (See Table 3-1 for signal descriptions.)
Figure 2-2 shows how an NSE subsystem can be formed using a host ASIC, a bank of Ayama 10000A devices and a bank of
SRAM devices. (See Table 3-1 for signal descriptions.) It presents an example of how the NSE subsystem is integrated in a switch
or router. The example also shows two possible ways of connecting the devices in the NSE subsystem. In the Associative set-
up, the host ASIC sends instructions to the NSE. Where applicable, the NSE drives the SRAM inputs and the SRAM then returns
the requested data to the host ASIC. In the Index set-up, the NSE’s SRAM address information is routed back to the host ASIC.
The host ASIC then interacts with the SRAM bank after it receives the result from the NSE.
FULI[6:0]/LHI_1[6:0]
CLK1X/CLK2X
LHI[6:0]/LHI_0[6:0]
PARERR_L
CLK_MODE
CMD[10:0]
DQ[71:0]
PAR[1:0]
Overview
ID[4:0]
PHS_L
CMDV
RST_L
EOT
ACK
BHI[2:0]
FULL
PIO Access
Command
Decode
Parity
and
Full Logic
CONFIDENTIAL
Figure 2-1. Ayama™ 10000A Block Diagram
CMD
Control and Configuration
Internal Registers
Block Associated
Internal Registers
Mask Array
Data Array
Compare / PIO Data
Arbitration
Logic
Controller
Interface
Control
Pipeline
SRAM
TAP
and
CYNSE10512A
CYNSE10256A
CYNSE10128A
OE_L
CE_L
ALE_L
SADR[N:0],
MULTI_HIT
FULO[1:0]/LHO_1[1:0]
LHO[1:0]/LHO_0[1:0]
WE_L
BHO[2:0]
SSF
SSV
TMS
TCK
TRST_L
TDI
TDO
23 for
CYNSE10128A
N = 25 for
CYNSE10512A,
24 for
CYNSE10256A,
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