CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 105

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
The Learn command is a pipelined operation and lasts for two CLK cycles. Figure 6-53, Figure 6-54 and Figure 6-55 show the
timing diagram of Learn operations with the address taken from the NFA or SRR register. Figure 6-54 and Figure 6-55 assume
that the device performing the Learn operation is not the last device in the table and will therefore have its LRAM bit set to 0. The
OE_L for the device with the LRAM bit set goes HIGH for two cycles for each Learn (one during the SRAM Write cycle and one
during the cycle before). The SRAM Write cycle latency from the second cycle of the instruction is shown in Table 6-15. The Learn
command also generates a Write cycle to the external SRAM (see Section 6.7, “SRAM PIO Access,” on page 113).
Note that mismatched entry-width Learn operation is not supported. For example, the result of a 72-bit Search miss stored in one
of the SRR registers cannot be used for a 144-bit Learn operation.
6.6.1
The Learn command in the Non-Enhanced mode supports x72 and x144 table widths. The operation uses the data stored in the
user selected CMPR register for writing to an entry in the Data array. Non-Enhanced mode Learn operation ignores the DQ bus
and cannot perform a write to the Mask array. The address for the target data entry is the INDEX field of the Next-free Address
(NFA) register.
Once the operation is completed the NFA register’s INDEX field is updated with next highest priority free entry in the Data array.
The LSB of each x72 entry is treated as a valid bit and used to indicate whether that entry is free (=0 (binary)) or not (=1 (binary)).
For a 144-bit entry, bit [72] and bit[0] must be set to the same value.
Note that Learn command for x144 entry width in Non-Enhanced can only be issued when all the tables in the device is of x144
table width.
6.6.2
The Learn command in the Enhanced mode supports all table widths (x72, x144, x288 and x576). The user can select whether
the data stored in the user selected CMPR register or the data presented in the DQ bus be used for the learn operation. The user
can also select to write to an entry in either the Data or Mask array. The address for the target entry is the INDEX field of the user-
selected Search Result Register (SRR). Each SRR is one-to-one associated to a Comparand (CMPR) register. So the selection
of the SRR is accomplished by selecting the corresponding (CMPR) register.
The SRR register is updated after a Search operation. Only the LSB of each entry is used, regardless of width, to indicate whether
that entry is free (=0 (binary)) or not (=1 (binary)).
Non-Enhanced Mode
Enhanced Mode
Table 6-14. Latency of SADR for different learn widths
Learn-key widths
x144
x288
x576
x72
CONFIDENTIAL
Latency of SADR field in CLK1X cycles
5+TLSZ
5+TLSZ
4+TLSZ
2+TLSZ
CYNSE10512A
CYNSE10256A
CYNSE10128A
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