CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 123

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
6.7.6
The following explains the SRAM Write operation accomplished through a table of up to 31 devices with the following parameter:
TLSZ = 10 (binary). The hardware diagram is shown in Figure 6-67. The following assumes that SRAM access is accomplished
through Ayama 10000A device number 0—the selected device. Figure 6-68 and Figure 6-69 show timing diagrams for device
number 0 and device number 30, respectively.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation, but the Write cycle appears at the SRAM
bus with the same latency as that of a Search instruction, as measured from the second cycle of the Write command.
• Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address with
• Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the Ayama 10000A device.
• Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the Ayama 10000A device.
DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. The host ASIC also supplies SADR[25:23] for CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for
CYNSE10128A on CMD[8:6] in this cycle.
Note. CMD[2] must be set to 0 for SRAM Write because burst WRITEs into the SRAM are not supported.
address with DQ[20:19] set to 10 to select the SRAM address.
Note. CMD[2] must be set to 0 for SRAM Write because burst WRITEs into the SRAM are not supported.
SRAM Write with Table(s) Consisting of up to 31 Devices
SADR[M:0]
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
ALE_L
CMDV
WE_L
OE_L
CE_L
ACK
SSV
M = 25 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A
SSF
TLSZ = 01 (binary), HLAT = XXX, LRAM = 1 (binary), LDEV = 1 (binary)
DQ
Figure 6-66. SRAM Write Timing of Device #7 in Block of Eight Devices
0
0
0
1
1
1
z
CONFIDENTIAL
Address
cycle
Write
1
A B
01
cycle
2
x
cycle
3
x
cycle
4
cycle
5
cycle
6
cycle
7
cycle
1
8
z
z
z
z
cycle
9
cycle
10
CYNSE10512A
CYNSE10256A
CYNSE10128A
0
1
1
1
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