AD9484BCPZ-500 Analog Devices Inc, AD9484BCPZ-500 Datasheet
AD9484BCPZ-500
Specifications of AD9484BCPZ-500
Related parts for AD9484BCPZ-500
AD9484BCPZ-500 Summary of contents
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FEATURES SNR = 47 dBFS 250 MHz at 500 MSPS IN ENOB of 7.5 bits 250 MHz at 500 MSPS (−1.0 dBFS) IN SFDR = 79 dBc 250 ...
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AD9484 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching ...
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SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 1. 1 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) INTERNAL REFERENCE VREF TEMPERATURE DRIFT ...
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AD9484 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table Parameter SNR f = 30.3 MHz 70.3 MHz 100.3 MHz 250.3 ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 3. Parameter 1 CLOCK INPUTS Logic Compliance Internal Common-Mode Bias Differential Input Voltage High Level Input ( Low Level Input (V ) ...
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AD9484 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 4. Parameter Maximum Conversion Rate Minimum Conversion Rate 1 CLK+ Pulse Width High ( CLK+ Pulse Width Low (t ) ...
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ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Electrical AVDD to AGND −0 +2.0 V DRVDD to DRGND −0 +2.0 V AGND to DRGND −0 +0.3 V AVDD to DRVDD −2 +2.0 V ...
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AD9484 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 7. Pin Function Descriptions Pin No. Mnemonic 1 0 AGND 30 34 39, AVDD 24, 47 DRVDD 1 8, 23, 48 DRGND 35 VIN+ ...
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Pin No. Mnemonic 14 D4+ 15 D5− 16 D5+ 17 D6− 18 D6+ 19 D7− 20 D7+ 21 OR− 22 OR+ 1 Tie AGND and DRGND to a common quiet ground plane. Description D4 True Output. D5 Complement Output. D5 ...
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AD9484 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate 500MSPS –10 30.3MHz AT –1.0dBFS SNR: 46.0dB ENOB: 7.5 BITS –20 SFDR: 82dBc –30 –40 –50 –60 –70 –80 –90 –100 0 20 ...
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SFDR (dBc), 30.3MHz 80 75 SFDR (dBc), 100.3MHz SNR (dBFS), 30.3MHz 50 SNR (dBFS), 100.3MHz 100 150 200 250 300 350 400 SAMPLE RATE (MSPS) Figure 10. SNR/SFDR vs. Sample Rate; 30.3 ...
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AD9484 100 IMD3 (dBFS SFDR (dBFS SFDR (dBc –90 –80 –70 –60 –50 –40 AMPLITUDE (dBFS) Figure 16. Two-Tone SFDR vs. Input Amplitude; 500 MSPS, 119.5 MHz, 122.5 MHz 90 ...
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EQUIVALENT CIRCUITS AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 20. Clock Inputs AVDD CML AVDD VIN+ 500Ω AVDD 500Ω SPI CONTROLLED VIN+ Figure 21. Analog Input DC Equivalent Circuit (V DRVDD 350Ω SCLK/DFS 30kΩ Figure 22. Equivalent SCLK/DFS, PDWN Input ...
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AD9484 THEORY OF OPERATION The AD9484 architecture consists of a front-end sample-and- hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 8-bit result in the digital correction logic. ...
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ANALOG INPUT ANALOG INPUT CLOCK INPUT CLOCK INPUT 1 50Ω RESISTORS ARE OPTIONAL. CLOCK INPUT CLOCK INPUT 1 50Ω RESISTORS ARE OPTIONAL. CLOCK INPUT CONSIDERATIONS For optimum performance, drive the AD9484 sample clock inputs (CLK+ and CLK−) with a differential ...
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AD9484 V CC OPTIONAL 0.1µF 1kΩ AD951x CLOCK CMOS DRIVER INPUT 1 1kΩ 50Ω 0.1µF 1 50Ω RESISTOR IS OPTIONAL. Figure 34. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) Clock Duty Cycle Considerations Typical high speed ADCs ...
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An example of the LVDS output using the ANSI standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on ...
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AD9484 AD9484 CONFIGURATION USING THE SPI The AD9484 SPI allows the user to configure the converter for specific functions or operations through a structured register space inside the ADC. This gives the user added flexibility to customize device operation depending ...
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Table 10. Serial Timing Definitions Parameter Minimum (ns CLK HIGH t 16 LOW t 1 EN_SDIO t 5 DIS_SDIO Table 11. Output Data Format ...
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AD9484 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table (see Table 12) has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), ...
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Addr. Bit 7 (Hex) Register Name (MSB) 10 Offset 0D TEST_IO (For user-defined mode only, set Bits[3:0] = 1000 Pattern 1 only 01 = toggle P1/ toggle P1/0000 11 = toggle P1/P2/ 0000 0F AIN_CONFIG 0 ...
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AD9484 Addr. Bit 7 (Hex) Register Name (MSB) 18 FLEX_VREF VREF select 00 = internal V (20 kΩ pull-down import V (0. 0 VREF pin export V (from internal reference ...
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... OUTLINE DIMENSIONS PIN 1 INDICATOR TOP VIEW 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9484BCPZ-500 −40°C to +85°C AD9484BCPZRL7-500 −40°C to +85°C AD9484-500EBZ RoHS Compliant Part. 8.10 0.60 MAX 8.00 SQ 7.90 0.60 MAX 43 42 0.50 BSC 7 ...
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AD9484 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09615-0-3/11(0) Rev Page ...