AD9484BCPZ-500 Analog Devices Inc, AD9484BCPZ-500 Datasheet - Page 19

• Manufacturer Part Number: AD9484BCPZ-500
• Description: IC ADC 8BIT 500MSPS 56LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9484BCPZ-500

• Sampling Rate: 500MSPS
• Input Channel Type: Differential, Single Ended
• Data Interface: Serial, SPI
• Supply Current: 283mA
• Digital Ic Case Style: LFCSP
• No. Of Pins: 56
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Resolution (bits): 8bit
• Number Of Elements: 1
• Resolution: 8Bit
• Architecture: Pipelined
• Input Type: Voltage
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 1.8V
• Single Supply Voltage (max): 1.9V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 720mW
• Differential Linearity Error: ±0.25LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Input Signal Type: Differential
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 10. Serial Timing Definitions
Parameter
t
t
t
t
t
t
t
t
t
Table 11. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
Minimum (ns)
5
2
40
5
2
16
16
1
5
Condition (V)
< −0.75 − 0.5 LSB
= −0.75
= 0
= 0.75
> 0.75 + 0.5 LSB
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling
edge (not shown in Figure 39)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 39)
Offset Binary Output Mode, D7± to D0±
0000 0000
0000 0000
1000 0000
1111 1111
1111 1111
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Twos Complement Mode, D7± to D0±
1000 0000
1000 0000
0000 0000
0111 1111
0111 1111
AD9484
OR±
1
0
0
0
1