AD9484BCPZ-500 Analog Devices Inc, AD9484BCPZ-500 Datasheet - Page 20

• Manufacturer Part Number: AD9484BCPZ-500
• Description: IC ADC 8BIT 500MSPS 56LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9484BCPZ-500

• Sampling Rate: 500MSPS
• Input Channel Type: Differential, Single Ended
• Data Interface: Serial, SPI
• Supply Current: 283mA
• Digital Ic Case Style: LFCSP
• No. Of Pins: 56
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Resolution (bits): 8bit
• Number Of Elements: 1
• Resolution: 8Bit
• Architecture: Pipelined
• Input Type: Voltage
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 1.8V
• Single Supply Voltage (max): 1.9V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 720mW
• Differential Linearity Error: ±0.25LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Input Signal Type: Differential
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map table (see Table 12) has eight
address locations. The memory map is roughly divided into
three sections: chip configuration register map (Address 0x00 to
Address 0x02), transfer register map (Address 0xFF), and ADC
functions register map (Address 0x08 to Address 0x2A).
The Addr. (Hex) column of the memory map indicates the register
address in hexadecimal, and the Default Value (Hex) column
shows the default hexadecimal value that is already written into
the register. The Bit 7 (MSB) column is the start of the default
hexadecimal value given. For example, Hexadecimal Address
0x2A, OVR_CONFIG, has a hexadecimal default value of 0x01.
This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0,
Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The
default value enables the OR± output. Overwriting this default so
that Bit 0 = 0 disables the OR± output. For more information on
this and other functions, consult the
Interfacing to High-Speed ADCs via SPI® user manual at
www.analog.com.
Table 12. Memory Map Register
Addr.
(Hex)
Chip Configuration Registers
00
01
02
Transfer Register
FF
ADC Functions Registers
08
AD9484
Register Name
CHIP_PORT_CONFIG
CHIP_ID
CHIP_GRADE
DEVICE_UPDATE
Modes
Bit 7
(MSB)
0
0
0
0
AN-877
Bit 6
LSB
first
0
0
0
Application Note,
Bit 5
Soft
reset
0
PDWN:
0 = full
(default)
1 =
standby
0
8-bit chip ID, Bits[7:0] = 0x6C
Rev. 0 | Page 20 of 24
Bit 4
1
0
0
00 = 500 MSPS
Speed grade:
Bit 3
1
0
0
RESERVED LOCATIONS
Undefined memory locations should not be written to other
than with the default values suggested in this data sheet. Addresses
that have values marked as 0 should be considered reserved and
have a 0 written into their registers during power-up.
DEFAULT VALUES
Coming out of reset, critical registers are preloaded with default
values. These values are indicated in Table 12. Other registers
do not have default values and retain the previous value when
exiting reset.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit. ” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit. ”
Bit 2
Soft
reset
X
0
Note that external PDWN pin
1
Internal power-down mode:
011 = normal (power-up)
000 = normal (power-up,
001 = full power-down
overrides this setting
010 = standby
Bit 1
LSB
first
X
0
default)
1
X
Bit 0
(LSB)
0
X
SW
transfer
1
Default
Value
(Hex)
0x18
Read
only
Read
only
0x00
0x00
Default Notes/
Comments
The nibbles
should be
mirrored by the
user so that LSB
or MSB first
mode registers
correctly,
regardless of
shift mode.
Default is a
unique chip ID,
different for
each device.
This is a read-
only register.
Child ID used to
differentiate
graded devices.
Synchronously
transfers data
from the master
shift register to
the slave.
Determines
various generic
modes of chip
operation.