LCMXO1200C-3BN256I Lattice, LCMXO1200C-3BN256I Datasheet - Page 3

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LCMXO1200C-3BN256I

Manufacturer Part Number
LCMXO1200C-3BN256I
Description
IC PLD 1200LUTS 211I/O 256CABGA
Manufacturer
Lattice
Datasheet

Specifications of LCMXO1200C-3BN256I

Programmable Type
*
Number Of Macrocells
*
Voltage - Input
*
Speed
*
Mounting Type
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1063

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Introduction
Lattice Semiconductor
MachXO Family Data Sheet
The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flex-
ible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, high-
security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and
careful design will provide the high pin-to-pin performance also associated with CPLDs.
®
The ispLEVER
design tools from Lattice allow complex designs to be efficiently implemented using the MachXO
family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools
use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in
the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design
for timing verification.
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