ICS9DB401CGLFT IDT, Integrated Device Technology Inc, ICS9DB401CGLFT Datasheet - Page 4

• Manufacturer Part Number: ICS9DB401CGLFT
• Description: IC BUFFER 4OUTPUT DIFF 28-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Buffer/Driverr

Specifications of ICS9DB401CGLFT

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9DB401CGLFT

Pin Description for OE_INV = 1
IDT
PIN #
ICS9DB401C
Four Output Differential Buffer for PCI Express
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
TM
1
2
3
4
5
6
7
8
9
/ICS
TM
Four Output Differential Buffer for PCI Express
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE1#
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
PD
SRC_STOP
HIGH_BW#
VDD
DIF_5#
DIF_5
OE6#
DIF_6#
DIF_6
VDD
OE_INV
IREF
GNDA
VDDA
PIN NAME
PIN TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Asynchronous active high input pin used to power down the
device. The internal clocks are disabled and the VCO is stopped.
Active high input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
4
DESCRIPTION
ICS9DB401C
REV E 03/18/08