ICS9DB401CGLFT IDT, Integrated Device Technology Inc, ICS9DB401CGLFT Datasheet - Page 5

• Manufacturer Part Number: ICS9DB401CGLFT
• Description: IC BUFFER 4OUTPUT DIFF 28-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Buffer/Driverr

Specifications of ICS9DB401CGLFT

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9DB401CGLFT

Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
IDT
T
Operating Supply Current
1
2
3
Tambient
ESD prot
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
Time from deassertion until outputs are >200 mV
Symbol
VDD_In
A
VDD_A
Modulation Frequency
Tcase
ICS9DB401C
Four Output Differential Buffer for PCI Express
Tdrive_SRC_STOP#
Powerdown Current
= 0 - 70°C; Supply Voltage V
Input Capacitance
TM
Input High Voltage
Clk Stabilization
Input High Current
Input Low Voltage
Input Low Current
V
V
Ts
Input Frequency
Input Frequency
Input Frequency
Pin Inductance
PLL Bandwidth
/ICS
PARAMETER
IL
IH
Tdrive_PD#
TM
Trise
Tfall
Four Output Differential Buffer for PCI Express
3.3V Logic Supply Voltage
3.3V Core Supply Voltage
Ambient Operating Temp
Storage Temperature
Input ESD protection
1,2
1
human body model
Input High Voltage
Case Temperature
Input Low Voltage
1
Parameter
I
SYMBOL
DD3.3ByPass
I
I
F
F
DD3.3PLL
fMOD
DD3.3PD
T
F
C
iBypass
iBypass
BW
V
L
C
V
I
I
STAB
I
iPLL
IL1
IL2
OUT
IH
pin
DD
IH
IN
IL
= 3.3 V +/-5%
input clock stabilization or de-
V
From V
assertion of PD# to 1st clock
V
all differential pairs tri-stated
IN
Full Active, C
IN
SRC_Stop# de-assertion
Bypass Mode (Revision
Bypass Mode (Revision
Output pin capacitance
DIF output enable after
DIF output enable after
= 0 V; Inputs with no pull-
= 0 V; Inputs with pull-up
Triangular Modulation
Rise time of PD# and
PLL Bandwidth when
PLL Bandwidth when
Fall time of PD# and
all diff pairs driven
PD# de-assertion
B/REV ID = 1H)
C/REV ID = 2H)
DD
CONDITIONS
SRC_STOP#
SRC_STOP#
Logic Inputs
3.3 V +/-5%
3.3 V +/-5%
up resistors
PLL_BW=0
PLL_BW=1
PLL Mode
V
Power-Up and after
resistors
GND-0.5
IN
2000
= V
Min
-65
L
0
= Full load;
DD
V
DD
Max
150
115
4.6
4.6
+0.5V
70
GND - 0.3
5
MIN
-200
1.5
2.4
0.7
50
30
-5
-5
2
0
0
Units
°
°C
°C
V
V
V
V
V
TYP
C
175
160
0.5
10
3
1
V
333.33
DD
MAX
200
175
200
400
300
0.8
3.4
1.4
40
33
15
5
4
7
4
4
1
5
5
+ 0.3
UNITS NOTES
MHz
MHz
MHz
MHz
MHz
kHz
mA
mA
mA
mA
ms
uA
uA
uA
nH
pF
pF
ns
us
ns
ns
V
V
ICS9DB401C
1,2
1,3
1,3
1
1
1
1
1
1
1
2
REV E 03/18/08