ICS9FG107AGLNT IDT, Integrated Device Technology Inc, ICS9FG107AGLNT Datasheet - Page 4

• Manufacturer Part Number: ICS9FG107AGLNT
• Description: IC FREQ TIMING GENERATOR 48TTSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS9FG107AGLNT

• Input: Clock, Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9FG107AGLNT

Pin Description (Continued)
IDT
Pins preceeded by * have 120 Kohm pull UP resistors
Pins preceeded by ** have 120 Kohm pull DOWN resistors
PIN #
ICS9FG107
Programmable FTG for Differential P4
TM
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
/ICS
TM
Programmable FTG for Differential P4
DIF_STOP#
SPREAD*
SEL14M_25M#**
OE_3*
DIF_3#
DIF_3
VDD
DIF_2#
DIF_2
OE_2**
GND
VDD
OE_1**
DIF_1#
DIF_1
VDD
DIF_0#
DIF_0
OE_0*
FS1**
DWNSPRD#*
IREF
GNDA
VDDA
PIN NAME
PIN TYPE
TM
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
TM
IN
IN
IN
IN
IN
IN
IN
IN
IN
CPU, PCI-Express & SATA Clocks
CPU, PCI-Express & SATA Clocks
Active low input to stop differential output clocks.
Asynchronous, active high input, with internal 120Kohm pull-up
resistor, to enable spread spectrum functionality.
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz,
0 = 25 MHz
Active high input for enabling output 3.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active high input for enabling output 2.
0 = tri-state outputs, 1= enable outputs
Ground pin.
Power supply, nominal 3.3V
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active high input for enabling output 0.
0 = tri-state outputs, 1= enable outputs
3.3V Frequency select latched input pin.
3.3V input that selects spread mode. This input is not latched at
power up.
0 = Down Spread, 1 = Center Spread
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
4
DESCRIPTION
ICS9FG107
REV F 08/21/07