ICS932S401EFT IDT, Integrated Device Technology Inc, ICS932S401EFT Datasheet - Page 5

• Manufacturer Part Number: ICS932S401EFT
• Description: IC TIMING CTRL HUB PROGR 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS932S401EFT

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 932S401EFT

Absolute Max
Current sinking at V
0921G—08/24/09
T
1
2
3
PLL outputs.
Electrical Characteristics - Input/Supply/Common Output Parameters
Tambient
ESD prot
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
Symbol
VDD_In
A
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm accuracy on
VDD_A
Low Threshold Input High
Operating Supply Current
Tcase
Low Threshold Input Low
Low-level Output Voltage
= 0 - 70°C; Supply Voltage V
Modulation Frequency
Clock/Data Rise Time
Clock/Data Fall Time
Ts
Powerdown Current
Input Capacitance
Input High Voltage
Clk Stabilization
Input Low Voltage
Input High Current
Input Low Current
Input Frequency
Pin Inductance
SMBus Voltage
PARAMETER
SCLK/SDATA
SCLK/SDATA
Tdrive_PD#
Trise_Pd#
Tfall_Pd#
Integrated
Circuit
Systems, Inc.
Voltage
Voltage
3.3V Logic Input Supply Voltage
3.3V Core Supply Voltage
Ambient Operating Temp
Storage Temperature
Input ESD protection
human body model
Case Temperature
OL
1
1,2
3
= 0.4 V
Parameter
1
SYMBOL
V
DD
I
I
I
V
DD3.3OP
V
DD3.3PD
OLSMBUS
T
V
PULLUP
C
T
T
C
V
L
C
V
I
I
IH_FS
IL_FS
STAB
I
IMAX
= 3.3 V +/-5%
F
RI2C
FI2C
IL1
IL2
OUT
INX
IH
pin
IH
IN
IL
i
Max. Voltage on SCLK/SDAT
@ I
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
V
assertion of PD# to 1st clock
V
all differential pairs tri-stated
IN
From V
IN
CPU output enable after
PULLUP
GND - 0.5
Output pin capacitance
3.3 V +/-5%, Full Load
= 0 V; Inputs with no pull-
= 0 V; Inputs with pull-up
Triangular Modulation
2000
all diff pairs driven
Min
PD# de-assertion
-65
PD# rise time of
PD# fall time of
0
CONDITIONS
X1 & X2 pins
Logic Inputs
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
up resistors
V
DD
V
resistors
DD
IN
Power-Up or de-
= 3.3 V
= V
V
V
DD
DD
DD
Max
150
115
+ 0.5V
+ 0.5V
70
5
V
V
Units
SS
SS
°C
°C
°
MIN
-200
V
V
V
0.7
C
30
-5
-5
2
4
- 0.3
- 0.3
14.31818
TYP
270
60
9
V
V
DD
DD
MAX
1000
0.35
350
300
300
0.8
1.8
5.5
0.4
90
15
33
5
7
5
6
5
5
5
+ 0.3
+ 0.3
UNITS NOTES
MHz
kHz
mA
mA
mA
mA
ms
uA
uA
uA
nH
pF
pF
pF
us
ns
ns
ns
ns
V
V
V
V
V
V
ICS932S401
1,2
3
1
1
1
1
1
1
1
2
1
1
1
1
1