IC PROGR DELAY CHIP 3.3V 32LQFP

MC100EP195BFAR2G

Manufacturer Part NumberMC100EP195BFAR2G
DescriptionIC PROGR DELAY CHIP 3.3V 32LQFP
ManufacturerON Semiconductor
Series100EP
TypeProgrammable Delay Chip
MC100EP195BFAR2G datasheet
 


Specifications of MC100EP195BFAR2G

InputECL, LVCMOS, LVTTLOutputECL
Frequency - Max1.2GHzVoltage - Supply3 V ~ 3.6 V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case32-LQFPFrequency-max1.2GHz
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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MC100EP195B
3.3V ECL Programmable
Delay Chip
Descriptions
The MC100EP195B is a Programmable Delay Chip (PDC)
designed primarily for clock deskewing and timing adjustment. It
provides variable delay of a differential NECL/PECL input transition.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 2. The delay
increment of the EP195B has a digitally selectable resolution of about
10 ps and a net range of up to 10.2 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
Table 6 and Figure 3.
The IN/IN inputs can accept LVPECL (SE of Diff), or LVDS level
signals. Because the EP195B is designed using a chain of multiplexers
it has a fixed minimum delay of 2.2 ns. An additional pin D10 is
provided for controlling Pins 14 and 15, CASCADE and CASCADE,
also latched by LEN, in cascading multiple PDCs for increased
programmable range. The cascade logic allows full control of multiple
PDCs. Switching devices from all “1” states on D[0:9] with SETMAX
LOW to all “0” states on D[0:9] with SETMAX HIGH will increase
the delay equivalent to “D0”, the minimum increment.
Select input pins D[10:0] may be threshold controlled by
combinations of interconnects between V
for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave V
and V
open. For ECL operation, short V
CF
EF
V
(Pins 7 and 8). For LVTTL level operation, connect a 1.5 V
EF
supply reference to V
and leave open V
CF
voltage to V
pin can be accomplished by placing a 2.2 kW resistor
CF
between V
and V
for a 3.3 V power supply.
CF
EE
The V
pin, an internally generated voltage supply, is available to
BB
this device only. For single−ended input conditions, the unused
differential input is connected to V
BB
V
may also rebias AC coupled inputs. When used, decouple V
BB
via a 0.01 mF capacitor and limit current sourcing or sinking
and V
CC
to 0.5 mA. When not used, V
should be left open.
BB
The 100 Series contains temperature compensation.
Features
Maximum Input Clock Frequency >1.2 GHz Typical
Programmable Range: 0 ns to 10 ns
Delay Range: 2.2 ns to 12.2 ns
10 ps Increments
PECL Mode Operating Range:
V
= 3.0 V to 3.6 V with V
CC
NECL Mode Operating Range:
V
= 0 V with V
= −3.0 V to −3.6 V
CC
EE
© Semiconductor Components Industries, LLC, 2008
September, 2008 − Rev. 1
(pin 7) and V
(pin 8)
EF
CF
and
CF
pin. The 1.5 V reference
EF
as a switching reference voltage.
BB
IN/IN Inputs Accept LVPECL, LVNECL, LVDS Levels
A Logic High on the EN Pin Will Force Q to Logic Low
D[10:0] Can Select Either LVPECL, LVCMOS, or
LVTTL Input Levels
V
Output Reference Voltage
BB
These are Pb−Free Devices
= 0 V
EE
1
http://onsemi.com
MARKING
DIAGRAMS*
MC100
EP195B
AWLYYWWG
LQFP−32
32
FA SUFFIX
1
CASE 873A
1
MC100
EP195B
32
1
ALYWG
QFN32
MN SUFFIX
CASE 488AM
A
= Assembly Location
WL, L
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
Publication Order Number:
MC100EP195B/D

MC100EP195BFAR2G Summary of contents

  • Page 1

    MC100EP195B 3.3V ECL Programmable Delay Chip Descriptions The MC100EP195B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable ...

  • Page 2

    D10 MC100EP195B Figure 1. 32−Lead LQFP Pinout (Top View ...

  • Page 3

    Table 1. PIN DESCRIPTION Pin Name I/O 23, 25, 26, 27, D[0:9] LVCMOS, LVTTL, 29, 30, 31, 32, ECL Input D[10] LVCMOS, LVTTL, ECL Input 4 IN LVPECL, LVDS 5 IN LVPECL, LVDS 6 V − BB ...

  • Page 4

    Table 2. CONTROL PIN Pin State EN LOW (Note 3) HIGH LEN LOW (Note 3) HIGH SETMIN LOW (Note 3) HIGH SETMAX LOW (Note 3) HIGH D10 LOW (Note 3) HIGH 3. Internal pulldown resistor will provide a logic LOW ...

  • Page 5

    Figure 2. Logic Diagram http://onsemi.com 5 ...

  • Page 6

    Table 6. THEORETICAL DELAY VALUES D(9:0) Value XXXXXXXXXX 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111 XXXXXXXXXX *Fixed minimum delay not included. SETMIN SETMAX ...

  • Page 7

    8000 V = −3 7000 6000 5000 4000 3000 2000 1000 0 0 100 Table 7. MAXIMUM RATINGS Symbol Parameter V Positive Mode Power Supply CC V ...

  • Page 8

    Table 8. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Negative Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ...

  • Page 9

    Table 9. 100EP DC CHARACTERISTICS, NECL Symbol Characteristic I Negative Power Supply Current EE (Note 11) V Output HIGH Voltage (Note 12 Output LOW Voltage (Note 12 Input HIGH Voltage (Single−Ended Input LOW Voltage ...

  • Page 10

    Table 10. AC CHARACTERISTICS V Symbol Characteristic f Maximum Frequency max V Output Voltage Amplitude outPP t Propagation Delay PLH D(0−10 SETMIN PHL D(0−10) = 1023, SETMAX D(0−10) ...

  • Page 11

    Table 10. AC CHARACTERISTICS Symbol Symbol Characteristic Characteristic V Input Voltage Swing PP (Differential Configuration) t Output Rise/Fall Time @ 50 MHz r t 20−80% (Q) f 20−80% (CASCADE) NOTE: Device will meet the specifications after thermal equilibrium has been ...

  • Page 12

    Need if Chip #3 is used D10 EP195B IN INPUT IN CHIP # expansion of the latch section of the block diagram is pictured in ...

  • Page 13

    Table 11. Delay Value of Two EP195B Cascaded VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2 INPUT FOR CHIP #1 D10 ...

  • Page 14

    Multi−Channel Deskewing The most practical application for EP195B is in multiple channel delay matching. Slight differences in impedance and cable length can create large timing skews within a high−speed system. To deskew multiple signal channels, each channel can Digital Data ...

  • Page 15

    ... Figure 9. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100EP195BFAG MC100EP195BFAR2G MC100EP195BMNG MC100EP195BMNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ...

  • Page 16

    −T− DETAIL −Z− −AB− −AC− SEATING PLANE 0.10 (0.004) AC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE ...

  • Page 17

    ... X 0.28 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...