MC100EP195BFAR2G ON Semiconductor, MC100EP195BFAR2G Datasheet
MC100EP195BFAR2G
Specifications of MC100EP195BFAR2G
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MC100EP195BFAR2G Summary of contents
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MC100EP195B 3.3V ECL Programmable Delay Chip Descriptions The MC100EP195B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable ...
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D10 MC100EP195B Figure 1. 32−Lead LQFP Pinout (Top View ...
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Table 1. PIN DESCRIPTION Pin Name I/O 23, 25, 26, 27, D[0:9] LVCMOS, LVTTL, 29, 30, 31, 32, ECL Input D[10] LVCMOS, LVTTL, ECL Input 4 IN LVPECL, LVDS 5 IN LVPECL, LVDS 6 V − BB ...
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Table 2. CONTROL PIN Pin State EN LOW (Note 3) HIGH LEN LOW (Note 3) HIGH SETMIN LOW (Note 3) HIGH SETMAX LOW (Note 3) HIGH D10 LOW (Note 3) HIGH 3. Internal pulldown resistor will provide a logic LOW ...
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Figure 2. Logic Diagram http://onsemi.com 5 ...
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Table 6. THEORETICAL DELAY VALUES D(9:0) Value XXXXXXXXXX 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111 XXXXXXXXXX *Fixed minimum delay not included. SETMIN SETMAX ...
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8000 V = −3 7000 6000 5000 4000 3000 2000 1000 0 0 100 Table 7. MAXIMUM RATINGS Symbol Parameter V Positive Mode Power Supply CC V ...
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Table 8. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Negative Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ...
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Table 9. 100EP DC CHARACTERISTICS, NECL Symbol Characteristic I Negative Power Supply Current EE (Note 11) V Output HIGH Voltage (Note 12 Output LOW Voltage (Note 12 Input HIGH Voltage (Single−Ended Input LOW Voltage ...
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Table 10. AC CHARACTERISTICS V Symbol Characteristic f Maximum Frequency max V Output Voltage Amplitude outPP t Propagation Delay PLH D(0−10 SETMIN PHL D(0−10) = 1023, SETMAX D(0−10) ...
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Table 10. AC CHARACTERISTICS Symbol Symbol Characteristic Characteristic V Input Voltage Swing PP (Differential Configuration) t Output Rise/Fall Time @ 50 MHz r t 20−80% (Q) f 20−80% (CASCADE) NOTE: Device will meet the specifications after thermal equilibrium has been ...
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Need if Chip #3 is used D10 EP195B IN INPUT IN CHIP # expansion of the latch section of the block diagram is pictured in ...
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Table 11. Delay Value of Two EP195B Cascaded VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2 INPUT FOR CHIP #1 D10 ...
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Multi−Channel Deskewing The most practical application for EP195B is in multiple channel delay matching. Slight differences in impedance and cable length can create large timing skews within a high−speed system. To deskew multiple signal channels, each channel can Digital Data ...
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... Figure 9. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100EP195BFAG MC100EP195BFAR2G MC100EP195BMNG MC100EP195BMNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ...
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−T− DETAIL −Z− −AB− −AC− SEATING PLANE 0.10 (0.004) AC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE ...
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... X 0.28 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...