LMX2541SQE2060E/NOPB National Semiconductor, LMX2541SQE2060E/NOPB Datasheet - Page 40

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LMX2541SQE2060E/NOPB

Manufacturer Part Number
LMX2541SQE2060E/NOPB
Description
IC PLL FREQ SYNTH W/VCO 36LLP
Manufacturer
National Semiconductor
Series
PowerWise®r
Type
Clock/Frequency Synthesizer (RF)r
Datasheet

Specifications of LMX2541SQE2060E/NOPB

Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:2
Differential - Input:output
No/No
Frequency - Max
2.24GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
36-LLP
Frequency-max
2.24GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LMX2541SQE2060ETR

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2.2 REGISTER R6
Register R6 has words that impact the output power of the RFout pin.
RFOUT[1:0] - RFout enable pin
This word works in combination with the EN_RFout Pin to control the state of the RFout pin.
DIVGAIN[3:0], VCOGAIN[3:0], and OUTTERM[3:0] - Power Controls for RFout
These three words may be programmed in a value from 0 to 15 and work in conjunction to control the output power level of the
RFout pin. Increasing any of these values increases the output power at the expense of higher current consumption of the buffer.
Although there may be more than one way to get the same output power, some combinations may have lower current. The typical
performance characteristics show these trade-offs. The default setting for all these bits is 12. The value of VCO_DIV determines
which two of these three words have an impact.
2.3 REGISTER R5
This register controls the fastlock mode which enables a wider loop bandwidth when the device is changing frequencies.
FL_TOC[13:0] -- Time Out Counter for FastLock
When the value of this word is 3 or less, FastLock time out counter is disabled, and the FLout pin can be used for general purpose
I/O. When this value is 4 or greater, the time out counter is engaged for the amount of phase detector cycles shown in the table
below.
When this count is active, the FLout Pin is grounded, the FastLock current is engaged, and the resistors R3 and R4 are also
potentially changed. The table below summarizes the bits that control various values in and out of FastLock.
FastLock State
Not Engaged
Engaged
TOC Value
16383
0
1
2
3
4
.
RFOUT
1 or 3
0
2
High Impedance
Grounded
>1 (Not Bypass)
FLout
1 (Bypass)
VCO_DIV
FLout Pin State
High Impedance
High
Low
Low
Low
Low
.
Charge Pump Current
EN_RFout Pin
Don't Care
Don't Care
High
Low
40
FL_CPG
CPG
Bits that Impact Power
OUTTERM, VCOGAIN
OUTTERM, DIVGAIN
16383 × 2 Phase Detector Cycles
Fastlock Engagement Time
4 × 2 Phase Detector Cycles
R3_LF Value
RFout Pin State
Always Engaged
FL_R3_LF
Engaged for
Engaged for
R3_LF
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
.
R4_LF Value
FL_R4_LF
R4_LF

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