ICS843101AGI-100LFT IDT, Integrated Device Technology Inc, ICS843101AGI-100LFT Datasheet - Page 11

• Manufacturer Part Number: ICS843101AGI-100LFT
• Description: IC SYNTHESIZER 100MHZ 16-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™, FemtoClock®r
• Type: Frequency Synthesizerr

Specifications of ICS843101AGI-100LFT

• Pll: Yes
• Input: LVCMOS, LVTTL, Crystal
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: No/Yes
• Frequency - Max: 100MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 100MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 843101AGI-100LFT

T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
IDT
R
I
C
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1k
tied from XTAL_IN to ground.
CLK I
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1k
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
RTT =
NPUTS
ERMINATION FOR
RYSTAL
ICS843101I-100
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER
ECOMMENDATIONS FOR
™
/ ICS
resistor can be tied from the CLK input to ground.
NPUT
((V
:
I
F
™
NPUT
FOUT
OH
IGURE
:
LVPECL FREQUENCY MARGINING SYNTHESIZER
ONTROL
+ V
:
OL
4A. LVPECL O
) / (V
1
resistor can be used.
P
CC
INS
3.3V LVPECL O
Z
Z
– 2)) – 2
:
o
o
= 50
= 50
U
NUSED
Z
o
50
UTPUT
I
NPUT
T
RTT
ERMINATION
UTPUT
50
P
V
CC
INS
resistor can be
FIN
- 2V
11
designed to drive 50
ance techniques should be used to maximize operating fre-
quency and minimize signal distortion. Figures 4A and 4B
show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FOUT
F
IGURE
4B. LVPECL O
Z
Z
o
o
= 50
= 50
ICS843101AGI-100 REV. A APRIL 26, 2007
transmission lines. Matched imped-
125
84
UTPUT
3.3V
125
84
T
ERMINATION
FIN