ICS843101AGI-100LFT IDT, Integrated Device Technology Inc, ICS843101AGI-100LFT Datasheet - Page 2

• Manufacturer Part Number: ICS843101AGI-100LFT
• Description: IC SYNTHESIZER 100MHZ 16-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™, FemtoClock®r
• Type: Frequency Synthesizerr

Specifications of ICS843101AGI-100LFT

• Pll: Yes
• Input: LVCMOS, LVTTL, Crystal
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: No/Yes
• Frequency - Max: 100MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 100MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 843101AGI-100LFT

T
IDT
F
The ICS843101I-100 features a fully integrated PLL and
therefore requires no external components for setting the loop
bandwidth. A 24MHz fundamental crystal is used as the input
to the on chip oscillator. The output of the oscillator is fed into
the pre-divider. In frequency margining mode, the 24MHz crystal
frequency is divided by 2 and a 12MHz reference frequency is
applied to the phase detector. The VCO of the PLL operates
over a range of 540MHz to 680MHz. The output of the M divider
is also applied to the phase detector.
The default mode for the ICS843101I-100 is 100MHz output
frequency using a 24MHz cr ystal. The output frequency
can be changed by placing the device into the margining mode
using the mode pin and using the serial interface to program the
M feedback divider. Frequency margining mode operation occurs
when the MODE input is HIGH. The phase detector and the M
divider force the VCO output frequency to be M times the
reference frequency by adjusting the VCO control voltage. Note
ABLE
UNCTIONAL
(
X
ICS843101I-100
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER
M
™
T
2
2
2
2
2
2
2
2
2
2
2
H
A
/ ICS
4
4
4
4
4
4
4
4
4
4
4
) z
L
1. F
™
P
LVPECL FREQUENCY MARGINING SYNTHESIZER
REQUENCY
r
- e
D
D
(
) P
2
2
2
2
2
2
2
2
2
2
2
v i
ESCRIPTION
d i
S_CLOCK
S_LOAD
r e
S_DATA
M
ARGIN
F
e r
q
R
u
F
e
e
e f
UNCTION
n
1
1
1
1
1
1
1
1
1
1
1
e r
c
2
2
2
2
2
2
2
2
2
2
2
y
n
c
(
M
e
H
T
) z
ABLE
D
F
v i
e
F
e
d i
IGURE
d
4
4
4
4
4
5
5
5
5
5
5
e
5
6
7
8
9
0
2
3
4
5
b
1
t
( r
S
M5 M4
a
c
M
S
t
k
H
1. S
ERIAL
)
Time
(
M
ERIAL
1
1
1
1
1
B
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
1
n i
-
L
D
1
0
0
0
0
1
1
0
0
0
0
M3
OADING
r a
1
0
0
1
1
1
1
0
0
1
1
a
1
0
1
0
1
0
1
0
1
0
1
a t
L
) y
0
0
0
0
0
2
1
1
1
1
1
1
OAD
M2
that for some values of M (either too high or too low), the PLL will
not achieve lock. The output of the VCO is scaled by an output
divider prior to being sent to the LVPECL output buffer. The divider
provides a 50% output duty cycle. The relationship between the
crystal input frequency, the M divider, the VCO frequency and
the output frequency is provided in Table 1. When changing back
from frequency margining mode to nominal mode, the device will
return to the default nominal configuration that will provide 100MHz
output frequency.
Serial operation occurs when S_LOAD is HIGH. Serial data
can be loaded in either the default mode or the frequency
margining mode. The 6-bit shift register is loaded by sampling
the S_DATA bits with the rising edge of S_CLOCK. After shifting
in the 6-bit M divider value, S_LOAD is transitioned from HIGH
to LOW which latches the contents of the shift-register into the
M divider control register. When S_LOAD is LOW, any transitions
of S_CLOCK or S_DATA are ignored.
(
V
O
M
5
5
5
5
5
6
6
6
6
6
6
C
4
5
6
7
8
0
1
2
3
4
6
PERATIONS
H
M1 M0
0
2
4
6
8
0
2
4
6
8
0
O
) z
D
v i
O
d i
u
p t
6
6
6
6
6
6
6
6
6
6
6
e
( r
t u
t
S
N
)
ICS843101AGI-100 REV. A APRIL 26, 2007
F
e r
O
(
M
q
u
1
1
1
1
1
1
9
9
9
9
9
u
p t
0
0
0
0
0
1
H
0
2
4
6
8
e
0
2
4
6
8
0
) z
t u
n
c
y
N
o
%
m
C
1 -
n i
1
8 -
6 -
4 -
2 -
2
4
6
8
h
l a
0
0
0 .
0 .
0 .
0 .
a
0 .
0 .
0 .
0 .
0 .
0 .
n
M
g
o
e
d
e