SI5367B-B-GQ Silicon Laboratories Inc, SI5367B-B-GQ Datasheet - Page 6

• Manufacturer Part Number: SI5367B-B-GQ
• Description: IC UP-PROG CLK MULTIPLR 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5367B-B-GQ

• Package / Case: 100-TQFP, 100-VQFP
• Pll: Yes with Bypass
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 4:5
• Differential - Input:output: Yes/Yes
• Frequency - Max: 808MHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 1.62 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 808MHz
• Mounting Style: SMD/SMT
• Number Of Outputs: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5367
1. Functional Description
The Si5367 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5367 accepts four clock inputs
ranging from 10 to 707 MHz and generates five
frequency-multiplied clock outputs ranging from 10 to
945 MHz and select frequencies to 1.4 GHz. The device
provides virtually any frequency translation combination
across this operating range. Independent dividers are
available for every input clock and output clock, so the
Si5367 can accept input clocks at different frequencies
and it can generate output clocks at different
frequencies. The Si5367 input clock frequency and
clock multiplication ratio are programmable through an
I
based software utility, DSPLLsim, that can be used to
determine the optimum PLL divider settings for a given
input frequency/clock multiplication ratio combination
that minimizes phase noise and power consumption.
This
www.silabs.com/timing.
The Si5367 is based on Silicon Laboratories' 3rd-
generation DSPLL
rate frequency synthesis in a highly integrated PLL
solution that eliminates the need for external VCXO and
loop filter components. The Si5367 PLL loop bandwidth
is digitally programmable and supports a range from
30 kHz to 1.3 MHz. The DSPLLsim software utility can
be used to calculate valid loop bandwidth settings for a
given input clock frequency/clock multiplication ratio.
The Si5367 monitors all input clocks for loss-of-signal
and provides a LOS alarm when it detects missing
pulses on its inputs.
6
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In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
frequency near its last value to maintain operation with
an internal state close to the last valid operating state.
The Si5367 has five differential clock outputs. The
signal format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, unused clock outputs can be powered down to
minimize power consumption. The phase difference
between the selected input clock and the output clocks
is adjustable in 200 ps increments for system skew
control. In addition, the phase of each output clock may
be adjusted in relation to the other output clocks. The
resolution varies from 800 ps to 2.2 ns depending on
the PLL divider settings. Consult the DSPLLsim
configuration software to determine the phase offset
resolution for a given input clock/clock multiplication
ratio combination. For system-level debugging, a
bypass mode is available which drives the output clock
directly from the input clock, bypassing the internal
DSPLL. The device is powered by a single 1.8 or 2.5 V
supply.
1.1. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for more
detailed information about the Si5367. The FRM can be
downloaded from www.silabs.com/timing.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. This utility can be downloaded
from www.silabs.com/timing.