SI5367B-B-GQ Silicon Laboratories Inc, SI5367B-B-GQ Datasheet - Page 9

• Manufacturer Part Number: SI5367B-B-GQ
• Description: IC UP-PROG CLK MULTIPLR 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5367B-B-GQ

• Package / Case: 100-TQFP, 100-VQFP
• Pll: Yes with Bypass
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 4:5
• Differential - Input:output: Yes/Yes
• Frequency - Max: 808MHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 1.62 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 808MHz
• Mounting Style: SMD/SMT
• Number Of Outputs: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Pin #
12
13
57
29
30
34
35
Pin Name
CS0_C3A
CS1_C4A
INT_ALM
CKIN4+
CKIN4–
CKIN2+
CKIN2–
Table 3. Si5367 Pin Descriptions (Continued)
I/O
I/O
O
I
I
Signal Level
LVCMOS
LVCMOS
MULTI
MULTI
Preliminary Rev. 0.3
Interrupt/Alarm Output Indicator.
This pin functions as a maskable interrupt output with
active polarity controlled by the INT_POL register bit.
The INT output function can be turned off by setting
INT_PIN = 0. If the ALRMOUT function is desired
instead on this pin, set ALRMOUT_PIN = 1 and
INT_PIN = 0.
0 = ALRMOUT not active.
1 = ALRMOUT active.
The active polarity is controlled by CK_BAD_POL. If no
function is selected, the pin tristates.
Input Clock Select/CKIN3 or CKIN4 Active Clock Indi-
cator.
If manual clock selection is chosen, and if
CKSEL_PIN = 1, the CKSEL pins control clock selection
and the CKSEL_REG bits are ignored.
If CKSEL_PIN = 0, the CKSEL_REG register bits control
this function and these inputs tristate. If these pins are
not functioning as the CS[1:0] inputs and auto clock
selection is enabled, then they serve as the CKIN_n
active clock indicator.
0 = CKIN3 (CKIN4) is not the active input clock
1 = CKIN3 (CKIN4) is currently the active input to the
PLL
The CKn_ACTV_REG bit always reflects the active clock
status for CKIN_n. If CKn_ACTV_PIN = 1, this status will
also be reflected on the CnA pin with active polarity con-
trolled by the CK_ACTV_POL bit. If
CKn_ACTV_PIN = 0, this output tristates.
This pin has a weak pull-down.
Clock Input 4.
Differential clock input. This input can also be driven with
a single-ended signal. CKIN4 serves as the frame sync
input associated with the CKIN2 clock when
CK_CONFIG_REG = 1.
Clock Input 2.
Differential input clock. This input can also be driven with
a single-ended signal.
CS[1:0]
00
01
10
11
Description
Active Input Clock
CKIN1
CKIN2
CKIN3
CKIN4
Si5367
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