LMX2316TMX/NOPB National Semiconductor, LMX2316TMX/NOPB Datasheet - Page 11

• Manufacturer Part Number: LMX2316TMX/NOPB
• Description: IC FREQ SYNTH 1.2GHZ 16-TSSOP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2316TMX/NOPB

• Pll: Yes
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: No/No
• Frequency - Max: 1.2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LMX2316TMX; *LMX2316TMX/NOPB; LMX2316TMX

1.0 Functional Description
(Continued)
10012713
FIGURE 1. Typical Lock Detect Circuit
1.3.3 Lock Detect Filter Calculation
The component values for the open drain lock detect filter can be determined after assessing the qualifications for an in-lock
condition. The in-lock condition can be specified as being a particular number (N) of consecutive reference cycles or duration (D)
wherein the phase detector phase error is some factor less than the reference period. In an example where the phase detector
reference period is 10 kHz, one might select the threshold for in-lock as occurring when 5 consecutive phase comparisons have
elapsed where the phase errors are a 1000 times shorter than the reference period (100 ns). Here, N = 5 and F = 1000.
For the lock detect filter shown in Figure 1, when used in conjunction with a open drain (active sink only) lock detect output, the
resistor value for R2 would be chosen to be a factor of F * R1. Thus, if resistor R1 were pulled low for only 1/1000th of the
reference cycle period, its “effective” resistance would be on par with R2. The two resistors for that duty cycle condition on
average appear to be two 1000x R1 resistors connected across the supply voltage with their common node voltage (Vc) at V
/2.
CC
Phase errors larger than 1/1000th of the reference cycle period would drag the average voltage of node Vc below V
/2 indicating
CC
an out-of-lock status. If the time constant of R2 * C1 is now calculated to be N * the reference period (500 µs), then the voltage
of node Vc would fall below V
/2 only after 5 consecutive phase errors whose average pulse width was greater than 100 ns.
CC
1.3.4 FastLock Modes
FastLock enables the designer to achieve both fast frequency transitions and good phase noise performance by dynamically
changing the PLL loop bandwidth. The FastLock modes allow wide band PLL fast locking with seemless transition to a low phase
noise narrow band PLL. Consistent gain and phase margins are maintained by simultaneously changing charge pump current
magnitude, counter values, and loop filter damping resistor. The four FastLock modes in Table 5 are similar to the technique used
in National Semiconductor’s LMX 233X series Dual Phase Locked Loops and are selected by F9, F10, and N19 when F8 is HIGH.
Modes 1 and 2 change loop bandwidth by a factor of two while modes 3 and 4 change the loop bandwidth by a factor of 4. Modes
1 and 2 increase charge pump magnitude by a factor of 4 and should use R2’=R2 for consistent gain and phase margin. Modes
3 and 4 increase charge pump magnitude and decrease the counter values by a factor of 4. R2’ =
⁄
R2 should be used for
1
3
consistent stability margin in modes 3 and 4. When F8 is LOW, the FastLock modes are disabled, F9 controls only the FL
output
o
= F9), and N19 determines the charge pump current magnitude (N19=LOW → ICP
= 250 µA, N19=HIGH → ICP
level (FL
=
o
o
o
1 mA).
11
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