LMX2316TMX/NOPB National Semiconductor, LMX2316TMX/NOPB Datasheet - Page 9

• Manufacturer Part Number: LMX2316TMX/NOPB
• Description: IC FREQ SYNTH 1.2GHZ 16-TSSOP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2316TMX/NOPB

• Pll: Yes
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: No/No
• Frequency - Max: 1.2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LMX2316TMX; *LMX2316TMX/NOPB; LMX2316TMX

1.0 Functional Description
1.3 FUNCTION AND INITIALIZATION LATCHES
Both the function and initialization latches write to the same registers. (See Section 2.1 DEVICE PROGRAMMING AFTER FIRST
APPLYING V
Function Description
F1. The Counter Reset enable mode bit F1, when activated, allows the reset of both N and R counters. Upon powering up, the
F1 bit needs to be disabled, then the N counter resumes counting in “close” alignment with the R counter. (The maximum error
is one prescalar cycle).
F2. Refer to Section 1.3.1 POWERDOWN OPERATION section.
F3–5. Controls output of FoLD pin. See FoLD truth table. See Table 4.
F6. Phase Detector Polarity. Depending upon VCO characteristics, F6 bit should be set accordingly. When VCO characteristics
are positive F6 should be set HIGH; When VCO characteristics are negative F6 should be set LOW
F7. Charge Pump TRI-STATE is set using bit F7. For normal operation this bit is set to zero.
F8. When the FastLock Enable bit is set the part is forced into one of the four FastLock modes. See description in Table 5,
FastLock Decoding.
F9. The FastLock Control bit determines the mode of operation when in FastLock (F8 = 1). When not in FastLock mode, FL
can be used as a general purpose output controlled by this bit. For F9 = 1, FL
5 for truth table.
F10. Timeout Counter Enable bit is set to 1 to enable the timeout counter. See Table 5 for truth table.
F11–14. FastLock Timeout Counter is set using bits F11-14. Table 6 for counter values.
F15–17. Function bits F15–F17 are for Test Modes, and should be set to 0 for normal use.
F18. Refer to Section 1.3.1 POWERDOWN OPERATION section.
F19. Function bit F19 is for a Test Mode, and should be set to 0 for normal use.
C1
CONTROL
REGISTER
0
FAST-
LEVEL
LOCK
F9
0
1
CC
C2
1
section for initialization latch description.)
COUNTER
RESET
COUNTER
TIMEOUT
ENABLE
F1
ENABELED
COUNTER
DISABLED
F10
RESET
RESET
RESET
POWER DOWN
TABLE 2. Mode Select Truth Table
TABLE 1. Programmable Modes
F2
(Continued)
COUNTER
TIMEOUT
F11–14
VALUE
POWERED
POWERED
POWER
DOWN
DOWN
UP
CONTROL
F3–5
FoLD
9
F15–F17
MODES
TEST
POLARITY
o
is HIGH and for F9 = 0, FL
DETECTOR
POLARITY
PD
NEGATIVE
F6
POSITIVE
PHASE
POWER
DOWN
MODE
F18
TRI-STATE
CP
F7
OPERATION
F19
TEST
MODE
10012707
o
TRI-STATE
TRI-STATE
NORMAL
is LOW. See Table
CP
FASTLOCK
ENABLE
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F8
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