MPC953FAR2 Freescale Semiconductor, MPC953FAR2 Datasheet

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MPC953FAR2

Manufacturer Part Number
MPC953FAR2
Description
IC PLL CLOCK DRIVER 32-LQFP
Manufacturer
Freescale Semiconductor
Type
Clock Driver, Fanout Distribution, Multiplexer , Zero Delay Bufferr
Datasheet

Specifications of MPC953FAR2

Pll
Yes
Input
LVCMOS, LVPECL, LVTTL
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
2:9
Differential - Input:output
Yes/No
Frequency - Max
110MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
110MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
MPC953FATR
Low Voltage PLL Clock Driver
targeted for high performance clock tree designs. With output frequencies
of up to 110MHz and output skews of 150ps the MPC953 is ideal for the
most demanding clock tree designs. The devices employ a fully
differential PLL design to minimize cycle–to–cycle and phase jitter.
external feedback input. These features make the MPC953 ideal for use
as a zero delay, low skew fanout buffer. The device performance has
been tuned and optimized for zero delay performance. The MR/OE input
pin will reset the internal counters and tristate the output buffers when
driven “high”.
filter components. All control inputs accept LVCMOS or LVTTL
compatible levels while the outputs provide LVCMOS levels with the
ability to drive terminated 50
50
device an effective fanout of 1:18. The device is packaged in a 7x7mm
32–lead LQFP package to provide the optimum combination of board
density and performance.
06/00
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
PECL_CLK
PECL_CLK
VCO_SEL
Motorola, Inc. 2000
Fully Integrated PLL
Output Frequency up to 110MHz in PLL Mode
Outputs Disable in High Impedance
LQFP Packaging
100ps Cycle–to–Cycle Jitter
The MPC953 is a 3.3V compatible, PLL based clock driver device
The MPC953 has a differential LVPECL reference input along with an
The MPC953 is fully 3.3V compatible and requires no external loop
BYPASS
FB_CLK
PLL_EN
MR/OE
lines, each of the MPC953 outputs can drive two traces giving the
(Int pull up)
(Int pull up)
(Int pull up)
(Int pull up)
(Int pull down)
(Int pull up)
transmission lines. For series terminated
Detector
Phase
1
LPF
Figure 1. Logic Diagram
200–500MHz
VCO
1
0
2
REV 3
1
0
PLL CLOCK DRIVER
32–LEAD LQFP PACKAGE
LOW VOLTAGE
MPC953
CASE 873A–02
4
FA SUFFIX
1
0
Order this document
by MPC953/D
7
QFB
Q0:6
Q7

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MPC953FAR2 Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver The MPC953 is a 3.3V compatible, PLL based clock driver device targeted for high performance clock tree designs. With output frequencies 110MHz and output skews of 150ps the ...

Page 2

MPC953 GNDO VCCO 27 QFB 28 MPC953 GNDO 29 PLL_EN 30 BYPASS 31 VCO_SEL Figure 2. 32–Lead Pinout (Top View) ABSOLUTE MAXIMUM RATINGS* Symbol Parameter V ...

Page 3

DC CHARACTERISTICS ( 3.3V 5%) Symbol Characteristic V IH Input HIGH Voltage LVCMOS Inputs V IL Input LOW Voltage LVCMOS Inputs V PP Peak–to–Peak Input Voltage PECL_CLK V CMR Common Mode ...

Page 4

MPC953 Power Supply Filtering The MPC953 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this ...

Page 5

The parallel combination of the 43 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will ...

Page 6

MPC953 –T– DETAIL –Z– –AB– SEATING –AC– PLANE 0.10 (0.004 DETAIL AD MOTOROLA OUTLINE ...

Page 7

ECLinPS and ECLinPS Lite DL140 — Rev 3 NOTES 7 MPC953 MOTOROLA ...

Page 8

MPC953 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out ...

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