MC145158DW2R2 Freescale Semiconductor, MC145158DW2R2 Datasheet - Page 6

• Manufacturer Part Number: MC145158DW2R2
• Description: IC SER-IN PLL FREQ SYNTH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Type: PLL Clock/Frequency Synthesizerr

Specifications of MC145158DW2R2

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 25MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 9 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Frequency-max: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MC145158DW2TR

INPUT PINS
f in
Frequency Input (Pin 1)
ac coupled into the device. For larger amplitude signals
(standard CMOS logic levels) dc coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (Pins 4, 5, 6)
possible divide values for the total reference divider. The
total reference divide values are as follows:
N0 – N9
N Counter Programming Inputs (Pins 11 – 20)
counter when it reaches the count of 0. N0 is the least signifi-
cant digit and N9 is the most significant. Pull–up resistors en-
sure that inputs left open remain at a logic 1 and require only
a SPST switch to alter data to the zero state.
A0 – A5
A Counter Programming Inputs
(Pins 23, 21, 22, 24, 25, 10)
require a logic 0 on the MC output (see Dual–Modulus
MC145151–2 through MC145158–2
6
f in is typically derived from a dual–modulus prescaler and is
Input to the positive edge triggered
These three inputs establish a code defining one of eight
The N inputs provide the data that is preset into the
The A inputs define the number of clock cycles of f in that
NOTE: N0 – N9, A0 – A5, and RA0 – RA2 have pull–up resistors that are not shown.
OSC out
RA2
OSC in
0
0
0
0
1
1
1
1
Reference Address Code
f in
PIN DESCRIPTIONS
RA1
0
0
1
1
0
0
1
1
RA0
Freescale Semiconductor, Inc.
0
1
0
1
0
1
0
1
RA2
RA1
RA0
For More Information On This Product,
6–BIT
A5
N and
A3 A2
A COUNTER
Divide
Divide
Value
Total
1024
2048
1160
MC145152–2 BLOCK DIAGRAM
128
256
512
Go to: www.freescale.com
64
8
A counters.
12 x 8 ROM REFERENCE DECODER
A0
12–BIT
N
CONTROL
LOGIC
R COUNTER
N0
12
Prescaling section). The A inputs all have internal pull–up
resistors that ensure that inputs left open will remain at a
logic 1.
OSC in , OSC out
Reference Oscillator Input/Output (Pins 27, 26)
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSC in to ground and OSC out to ground.
OSC in may also serve as the input for an externally–gener-
ated reference signal. This signal is typically ac coupled to
OSC in , but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC out .
OUTPUT PINS
Phase Detector B Outputs (Pins 7, 8)
for a loop–error signal.
leading, then error information is provided by V pulsing low.
lagging, then error information is provided by R pulsing low.
period when both pulse low in phase.
MC
Dual–Modulus Prescale Control Output (Pin 9)
controlling an external dual–modulus prescaler. The MC
level will be low at the beginning of a count cycle and will
remain low until the
programmed value. At this time, MC goes high and remains
high until the
down from its programmed value (N – A additional counts
since both
R , V
R remains essentially high.
V remains essentially high.
V and R remain high except for a small minimum time
These pins form an on–chip reference oscillator when con-
These phase detector outputs can be combined externally
If the frequency f V is greater than f R or if the phase of f V is
If the frequency f V is less than f R or if the phase of f V is
If the frequency of f V = f R and both are in phase, then both
Signal generated by the on–chip control logic circuitry for
10–BIT
N2
N4 N5
N COUNTER
N and
N counter has counted the rest of the way
N7
A counter has counted down from its
A are counting down during the first
N9
DETECTOR
DETECT
PHASE
LOCK
MOTOROLA
LD
MC
V
R