MPC962305D-1 Freescale Semiconductor, MPC962305D-1 Datasheet

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MPC962305D-1

Manufacturer Part Number
MPC962305D-1
Description
IC CLOCK BUFFER 1:5 8-SOIC
Manufacturer
Freescale Semiconductor
Type
Fanout Distribution, Spread Spectrum Clock Generator, Zero Delay Bufferr
Datasheet

Specifications of MPC962305D-1

Pll
Yes
Input
LVCMOS
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
1:5
Differential - Input:output
No/No
Frequency - Max
133.33MHz
Divider/multiplier
No/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Frequency-max
133MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Cost 3.3 V Zero Delay Buffer
clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one
reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin
version of the MPC962309 which drives five outputs with one reference input.
The -1H versions of these devices have higher drive than the -1 devices and
can operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs
which lock to an input clock presented on the REF pin. The PLL feedback is
on-chip and is obtained from the CLOCKOUT pad.
Features
Functional Description
trolled by the Select Inputs as shown in
MPC962309. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied
to the outputs for chip and system testing purposes.
state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0 µA of current draw for the device. The PLL
shuts down in one additional case as shown in
situation, the difference between the output skews of two devices will be less than 700 ps.
less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps.
The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and MPC962309-1H,
are available to provide faster rise and fall times of the base device.
© Motorola, Inc. 2004
The MPC962309 is a zero delay buffer designed to distribute high-speed
The MPC962309 has two banks of four outputs each, which can be con-
The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this
Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this
All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to be
The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information page.
1:5 LVCMOS zero-delay buffer (MPC962305)
1:9 LVCMOS zero-delay buffer (MPC962309)
Zero input-output propagation delay
Multiple low-skew outputs
250 ps max output-output skew
700 ps max device-device skew
Supports a clock I/O frequency range of 10 MHz to 133 MHz,
compatible with CPU and PCI bus frequencies
Low jitter, 200 ps max cycle-cycle, and compatible with Pentium
systems
Test Mode to bypass PLL (MPC962309 only. See “Select Input Decoding”)
8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin
TSSOP package (MPC962309)
Single 3.3 V supply
Ambient temperature range: –40°C to +85°C
Compatible with the CY2305, CY23S05, CY2309, CY23S09
Spread spectrum compatible
Freescale Semiconductor, Inc.
Table 3.Select Input Decoding for
For More Information On This Product,
Table 3.Select Input Decoding for
Go to: www.freescale.com
®
based
MPC962309.
16-LEAD TSSOP PACKAGE
MPC962305
MPC962309
8-LEAD TSSOP PACKAGE
16-LEAD SOIC PACKAGE
8-LEAD SOIC PACKAGE
CASE 751B-05
CASE 948F-01
CASE 948J-01
CASE 751-06
DT SUFFIX
DT SUFFIX
D SUFFIX
D SUFFIX
Order number: MPC962305
Rev 5, 08/2004

Related parts for MPC962305D-1

MPC962305D-1 Summary of contents

Page 1

... Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low-Cost 3.3 V Zero Delay Buffer The MPC962309 is a zero delay buffer designed to distribute high-speed clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin version of the MPC962309 which drives five outputs with one reference input ...

Page 2

... Freescale Semiconductor, Inc. Block Diagram PLL REF S2 Select Input Decoding S1 Table 1. Pin Description for MPC962309 Pin Signal 1 1 REF 2 2 CLKA1 3 2 CLKA2 GND 6 2 CLKB1 7 2 CLKB2 CLKB3 11 2 CLKB4 12 GND CLKA3 15 2 CLKA4 16 2 CLKOUT Table 2. Pin Description for MPC962305 ...

Page 3

... Freescale Semiconductor, Inc. MPC962305 MPC962309 Table 3. Select Input Decoding for MPC962309 S2 S1 CLOCK A1– Three-State 0 1 Driven 1 0 Driven 1 1 Driven 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output ...

Page 4

... Freescale Semiconductor, Inc. Table 7. Switching Characteristics for MPC962305-1 and MPC962309-1 Industrial Temperature Devices Parameter Name t Output Frequency 1 2 ÷ t Duty Cycle = Rise Time Fall Time Output to Output Skew 5 t Delay, REF Rising Edge CLKOUT Rising Edge t Delay, REF Rising Edge to 6B ...

Page 5

... Freescale Semiconductor, Inc. MPC962305 MPC962309 t 5 The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 1. Output-to-Output Skew 100 The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 3 ...

Page 6

... DD 0.1 µF OUTPUTS V DD GND GND 0.1 µF Test Circuit for all parameters except t 8 Table 9. Ordering Information Ordering Code MPC962305D-1 MPC962305D-1R2 MPC962305D-1H MPC962305D-1HR2 MPC962305DT-1H MPC962305DT-1HR2 MPC962309D-1 MPC962309D-1R2 MPC962309D-1H MPC962309D-1HR2 MPC962309DT-1H MPC962309DT-1HR2 TIMING SOLUTIONS 0.1 µF CLK OUT C LOAD 0.1 µF ...

Page 7

... Freescale Semiconductor, Inc. MPC962305 MPC962309 0. SEATING PLANE 0. 0. STYLE 1: STYLE 2: PIN 1. EMITTER PIN 1. COLLECTOR, DIE COLLECTOR 2. COLLECTOR COLLECTOR 3. COLLECTOR EMITTER 4. COLLECTOR EMITTER 5. BASE BASE 0. EMITTER BASE 7. BASE EMITTER 6.2 8. EMITTER PIN'S 5.8 NUMBER STYLE 5: STYLE PIN 1. DRAIN PIN 1. SOURCE 2. DRAIN 2. DRAIN 3 ...

Page 8

... Freescale Semiconductor, Inc. K 0.15 (0.006 L PIN 1 IDENT. 1 0.15 (0.006 -V- C 0.10 (0.004) G -T- D SEATING PLANE TIMING SOLUTIONS PACKAGE DIMENSIONS DT SUFFIX 8-LEAD TSSOP PACKAGE CASE 948J-01 ISSUE O REF 8x 0.10 (0.004 -U- SECTION N 0.25 (0.010 DETAIL E SEE DETAIL E H CASE 948J-01 ISSUE O 8 For More Information On This Product, Go to: www ...

Page 9

... Freescale Semiconductor, Inc. MPC962305 MPC962309 K 0.15 (0.006 L PIN 1 IDENT. 1 0.15 (0.006 0.10 (0.004) -T- SEATING D PLANE MOTOROLA PACKAGE DIMENSIONS DT SUFFIX 16-LEAD TSSOP PACKAGE CASE 948F-01 ISSUE O REF 16X 0.10 (0.004 SECTION N-N - 0.25 (0.010 - DETAIL E H DETAIL E G CASE 948F-01 ISSUE O 9 For More Information On This Product, Go to: www ...

Page 10

... Freescale Semiconductor, Inc. TIMING SOLUTIONS NOTES 10 For More Information On This Product, Go to: www.freescale.com MPC962305 MPC962309 MOTOROLA ...

Page 11

... Freescale Semiconductor, Inc. MPC962305 MPC962309 MOTOROLA NOTES 11 For More Information On This Product, Go to: www.freescale.com TIMING SOLUTIONS ...

Page 12

... Freescale Semiconductor, Inc. Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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