DS3234S# Maxim Integrated Products, DS3234S# Datasheet - Page 17

• Manufacturer Part Number: DS3234S#
• Description: IC RTC W/TCXO 20-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/TCXO/Crystalr

Specifications of DS3234S#

• Memory Size: 2K (256 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Function: Clock/Calendar/Alarm/Battery Backup/Interrupt
• Rtc Memory Size: 256 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (4-Wire, SPI)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 0: Battery-Backed Temperature Conversion
Disable (BB_TD). The battery-backed tempconv dis-
able bit prevents automatic temperature conversions
when the device is powered by the V
reduces the battery current at the expense of frequen-
cy accuracy.
The SRAM address register provides the 8-bit address
of the 256-byte memory array. The desired memory
address should be written to this register before the
data register is accessed. The contents of this register
are incremented automatically if the data register is
accessed more than once during a single transfer.
When the contents of the address register reach 0FFh,
the next access causes the register to roll over to 00h.
The SRAM data register provides the data to be written
to or the data read from the 256-byte memory array.
During a read cycle, the data in this register is that
found in the memory location in the SRAM address reg-
ister (18h/98h). During a write cycle, the data in this reg-
ister is placed in the memory location in the SRAM
address register (18h/98h). When the SRAM data regis-
ter is read or written, the internal register pointer
remains at 19h/99h and the SRAM address register
increments after each byte that is read or written, allow-
ing multibyte transfers.
*POR is defined as the first application of power to the device, either V
Note: These registers do not default to any specific value.
NAME:
NAME:
NAME:
POR*:
SRAM Data Register (19h/99h)
BIT 7
BIT 7
BIT 7
D7
A7
0
0
SRAM Address Register
Temperature Control
Extremely Accurate SPI Bus RTC with
Register (13h/93h)
BIT 6
BIT 6
BIT 6
D6
A6
0
0
____________________________________________________________________
BAT
BIT 5
BIT 5
BIT 5
(18h/98h)
D5
A5
0
0
supply. This
Integrated Crystal and SRAM
BIT 4
BIT 4
BIT 4
D4
A4
0
0
The DS3234 provides a 4-wire SPI serial data bus to com-
municate in systems with an SPI host controller. The
DS3234 supports both single byte and multiple byte data
transfers for maximum flexibility. The DIN and DOUT pins
are the serial data input and output pins, respectively.
The CS input is used to initiate and terminate a data
transfer. The SCLK pin is used to synchronize data move-
ment between the master (microcontroller) and the slave
devices (see Table 3). The shift clock (SCLK), which is
generated by the microcontroller, is active only during
address and data transfer to any device on the SPI bus.
Input data (DIN) is latched on the internal strobe edge
and output data (DOUT) is shifted out on the shift edge
(Figure 2). There is one clock for each bit transferred.
Address and data bits are transferred in groups of eight.
Figure 2. Serial Clock as a Function of Microcontroller Clock-
Polarity Bit
BAT
DATA LATCH (WRITE/INTERNAL STROBE)
DATA LATCH (WRITE/INTERNAL STROBE)
NOTE 1: CPHA BIT POLARITY (IF APPLICABLE) MAY NEED TO BE SET ACCORDINGLY.
NOTE 2: CPOL IS A BIT SET IN THE MICROCONTROLLER'S CONTROL REGISTER.
NOTE 3: DOUT REMAINS AT HIGH IMPEDANCE UNTIL 8 BITS OF DATA ARE READY TO BE
or V
BIT 3
BIT 3
BIT 3
Temperature Control (13h/93h)
D2
A2
0
0
SHIFTED OUT DURING A READ.
CC
.
SHIFT DATA OUT (READ)
SHIFT DATA OUT (READ)
SCLK WHEN CPOL = 0
SCLK WHEN CPOL = 1
SRAM Address (18h/98h)
BIT 2
BIT 2
BIT 2
D1
A1
0
0
SRAM Data (19h/99h)
CS
SPI Serial Data Bus
BIT 1
BIT 1
BIT 1
D1
A1
0
0
BB_TD
BIT 0
BIT 0
BIT 0
D0
A0
0
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