DS3234S# Maxim Integrated Products, DS3234S# Datasheet - Page 18

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DS3234S#

Manufacturer Part Number
DS3234S#
Description
IC RTC W/TCXO 20-SOIC
Manufacturer
Maxim Integrated Products
Type
Clock/Calendar/TCXO/Crystalr
Datasheet

Specifications of DS3234S#

Memory Size
2K (256 x 8)
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
SPI, 3-Wire Serial
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Function
Clock/Calendar/Alarm/Battery Backup/Interrupt
Rtc Memory Size
256 Byte
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Rtc Bus Interface
Serial (4-Wire, SPI)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
Address and data bytes are shifted MSB first into the
serial data input (DIN) and out of the serial data output
(DOUT). Any transfer requires the address of the byte
to specify a write or read, followed by one or more
bytes of data. Data is transferred out of the DOUT pin
for a read operation and into the DIN for a write opera-
tion (Figures 3 and 4).
Table 3. SPI Pin Function
* CPOL is the clock-polarity bit set in the control register of the host microprocessor.
** DOUT remains at high impedance until 8 bits of data are ready to be shifted out during a read.
Figure 3. SPI Single-Byte Write
Figure 4. SPI Single-Byte Read
18
Disable
Write
Read
Read Invalid Location
____________________________________________________________________
DOUT
SCLK
DIN
CS
DOUT
SCLK
MODE
DIN
CS
HIGH IMPEDANCE
HIGH IMPEDANCE
R/W
R/W
A6
A6
A5
A5
CS
H
L
L
L
A4
A4
A3
A3
*CPOL = 1, SCLK Rising
CPOL = 0, SCLK Falling
CPOL = 1, SCLK Falling
CPOL = 0, SCLK Rising
A2
A2
Input Disabled
Don’t Care
A1
A1
SCLK
A0
A0
D7
D7
The address byte is always the first byte entered after
CS is driven low. The most significant bit of this byte
determines if a read or write takes place. If the MSB is
0, one or more read cycles occur. If the MSB is 1, one
or more write cycles occur.
D6
D6
D5
D5
Input Disabled
Data Bit Latch
Don’t Care
D4
D4
DIN
X
D3
D3
D2
D2
D1
D1
Next Data Bit Shift**
D0
High Impedance
High Impedance
High Impedance
D0
DOUT

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