DS3234S# Maxim Integrated Products, DS3234S# Datasheet - Page 19

• Manufacturer Part Number: DS3234S#
• Description: IC RTC W/TCXO 20-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/TCXO/Crystalr

Specifications of DS3234S#

• Memory Size: 2K (256 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Function: Clock/Calendar/Alarm/Battery Backup/Interrupt
• Rtc Memory Size: 256 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (4-Wire, SPI)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data transfers can occur one byte at a time or in multi-
ple-byte burst mode. After CS is driven low, an address
is written to the DS3234. After the address, one or more
data bytes can be written or read. For a single-byte
transfer, one byte is read or written and then CS is dri-
ven high. For a multiple-byte transfer, however, multiple
bytes can be read or written after the address has been
written (Figure 5). Each read or write cycle causes the
RTC register address to automatically increment, which
continues until the device is disabled. The address
wraps to 00h after incrementing to 13h (during a read)
and wraps to 80h after incrementing to 93h (during a
write). An updated copy of the time is loaded into the
user buffers upon the falling edge of CS and each time
the address pointer increments from 13h to 00h.
Because the internal and user copies of the time are
only synchronized on these two events, an alarm condi-
tion can occur internally and activate the INT/SQW pin
independently of the user data.
Figure 5. SPI Multiple-Byte Burst Transfer
WRITE
READ
SCLK
DOUT
DIN
DIN
CS
HIGH IMPEDANCE
Extremely Accurate SPI Bus RTC with
ADDRESS
ADDRESS
BYTE
BYTE
____________________________________________________________________
DATA BYTE 0
BYTE 0
DATA
Integrated Crystal and SRAM
DATA BYTE 1
BYTE 1
DATA
If the SRAM is accessed by reading (address 19h) or
writing (address 99h) the SRAM data register, the con-
tents of the SRAM address register are automatically
incremented after the first access, and all data cycles
will use the SRAM data register.
The DS3234 package contains a quartz tuning-fork
crystal. Pick-and-place equipment can be used, but
precautions should be taken to ensure that excessive
shock and vibration are avoided. Exposure to reflow is
limited to 2 times maximum. Ultrasonic cleaning should
be avoided to prevent damage to the crystal.
Avoid running signal traces under the package, unless
a ground plane is placed between the package and the
signal line. All N.C. (no connect) pins must be connect-
ed to ground.
Handling, PC Board Layout,
DATA BYTE N
BYTE N
DATA
and Assembly
19