MAXQ3183-RAN+ Maxim Integrated Products, MAXQ3183-RAN+ Datasheet - Page 84

• Manufacturer Part Number: MAXQ3183-RAN+
• Description: IC AFE POLYPHASE MULTI 28TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAXQ3183-RAN+

• Number Of Channels: 8
• Power (watts): 140mW
• Voltage - Supply, Analog: 3.6V
• Voltage - Supply, Digital: 3.6V
• Package / Case: 28-TSSOP
• For Use With: MAXQ3183-KIT - KIT EV REFRNC DSIGN FOR MAXQ3183
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Bits: -
• Other names: 90-M3183+RAN

Low-Power, Multifunction, Polyphase AFE
with Harmonics and Tamper Detect
This register is a mirror of a CPU register in the MAXQ3183. This register should not be modified by supervisory
code.
This register specifies the number of system clock cycles between consecutive ADC conversions. It defaults to
0x167 (359 decimal), which specifies 360 CPU clock cycles between conversions. This register is a mirror of a CPU
register in the MAXQ3183.
84
Bit:
Name:
Reset:
Bit:
Name:
Reset:
Bit:
Name:
Reset:
BIT
5:4
______________________________________________________________________________________
7
6
3
2
1
0
ADCASD
ADCCD
ADCRY
ADCBY
ADCIE
NAME
ADCE
ARBE
ADCASD
15
—
7
0
7
Disable ADC Automatic Shutdown. Normally, the ADC analog section is powered off following a
conversion to conserve power. If this bit is set, the ADC leaves the analog section powered on
following a conversion.
ADC Data Ready. When a conversion is complete, this bit is set to indicate that data is available. This
bit generates an interrupt if ADCIE is set.
ADC Clock Divider. Sets the division ratio between the CPU master and ADC clock.
00 = divide by 1
01 = divide by 2
10 = divide by 4
11 = reserved
ADC Busy. When set, a single ADC conversion cycle is in progress. The bit is cleared on the
conclusion of the conversion cycle.
ADC Interrupt Enable. If set, the ADC interrupts the CPU at the completion of a conversion cycle.
Reference Buffer Enable. If set, the reference buffer is enabled to drive the REFO pin.
ADC Enable. If set, the ADC hardware is activated.
ADCRY
14
—
6
0
6
13
—
5
5
ADCCD
0x0
ADC Conversion Rate High Byte
ADC Conversion Rate Low Byte
12
—
4
4
ADC Conversion Rate (R_ADCRATE) (0x04E)
0x67
FUNCTION
ADCBY
ADC Configuration (R_ACFG) (0x04C)
11
—
3
0
3
ADCIE
Hardware Mirror Registers
10
—
2
1
2
ARBE
—
1
1
9
1
ADCE
0
1
8
1
0