AD73322LAR-REEL Analog Devices Inc, AD73322LAR-REEL Datasheet - Page 11

• Manufacturer Part Number: AD73322LAR-REEL
• Description: IC ANALOG FRONT END DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322LAR-REEL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-SOIC (7.5mm Width)
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.3V
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Not Compliant

FUNCTIONAL DESCRIPTION
Encoder Channels
Both encoder channels consist of a pair of inverting op amps
with feedback connections that can be bypassed if required, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part of
the sigma-delta ADC, also performs critical system-level filtering.
Due to the high level of oversampling, the input antialias require-
ments are reduced such that a simple single pole RC stage is
sufficient to give adequate attenuation in the band of interest.
Programmable Gain Amplifier
Each encoder section’s analog front end comprises a switched
capacitor PGA, which also forms part of the sigma-delta modula-
tor. The SC sampling frequency is DMCLK/8. The PGA, whose
programmable gain settings are shown in Table III, may be used
to increase the signal level applied to the ADC from low output
sources such as microphones, and can be used to avoid placing
external amplifiers in the circuit. The input signal level to the
sigma-delta modulator should not exceed the maximum input
voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in control register D.
IGS2
0
0
0
0
1
1
1
1
ADC
Both ADCs consist of an analog sigma-delta modulator and a
digital antialiasing decimation filter. The sigma-delta modu-
lator noise-shapes the signal and produces 1-bit samples at a
DMCLK/8 rate. This bitstream, representing the analog input
signal, is input to the antialiasing decimation filter. The decimation
filter reduces the sample rate and increases the resolution.
Analog Sigma-Delta Modulator
The AD73322L’s input channels employ a sigma-delta conversion
technique, which provides a high resolution 16-bit output with
system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73322L, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to F
(Figure 7a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
Table III. PGA Settings for the Encoder Channel
IGS1
0
0
1
1
0
0
1
1
IGS0
0
1
0
1
0
1
0
1
S
/2 = DMCLK/16
Gain (dB)
0
6
12
18
20
26
32
38
interest to an out-of-band position (Figure 7b). The combina-
tion of these techniques, followed by the application of a digital
filter, sufficiently reduces the noise in band to ensure good
dynamic performance from the part (Figure 7c).
Figure 7 shows the various stages of filtering that are employed
in a typical AD73322L application. In Figure 7a we see the trans-
fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes
care of any signals that could be aliased by the sampling fre-
quency. This also shows the major difference between the initial
oversampling rate and the bandwidth of interest. In Figure 7b,
the signal and noise-shaping responses of the sigma-delta modu-
lator are shown. The signal response provides further rejection
of any high frequency signals while the noise-shaping will push
the inherent quantization noise to an out-of-band position. The
detail of Figure 7c shows the response of the digital decimation
filter (Sinc-cubed response) with nulls every multiple of DMCLK/
256, which corresponds to the decimation filter update rate
for a 64 kHz sampling. The nulls of the Sinc3 response corre-
spond with multiples of the chosen sampling frequency. The
final detail in Figure 7d shows the application of a final anti-
alias filter in the DSP engine. This has the advantage of being
implemented according to the user’s requirements and available
MIPS. The filtering in Figures 7a through 7c is implemented in
the AD73322L.
INTEREST
INTEREST
INTEREST
BAND
BAND
BAND
OF
OF
OF
NOISE SHAPING
DIGITAL FILTER
a.
b.
c.
AD73322L
DMCLK/16
DMCLK/16
DMCLK/16
F
F
F
S
S
S
/2
/2
/2