AD73322LAR-REEL Analog Devices Inc, AD73322LAR-REEL Datasheet - Page 24

• Manufacturer Part Number: AD73322LAR-REEL
• Description: IC ANALOG FRONT END DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322LAR-REEL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-SOIC (7.5mm Width)
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.3V
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Not Compliant

AD73322L
DC2
0
0
0
0
1
1
1
1
PERFORMANCE
As the AD73322L is designed to provide high performance, low
cost conversion, it is important to understand the means by
which this high performance can be achieved in a typical appli-
cation. This section will, by means of spectral graphs, outline
the typical performance of the device and highlight some of the
options available to users in achieving their desired sample rate,
either directly in the device or by doing some post-processing in
the DSP, while also showing the advantages and disadvantages
of the different approaches.
Encoder Section
The AD73322L offers a variable sampling rate from a fixed
MCLK frequency—with 64 kHz, 32 kHz, 16 kHz and 8 kHz
being available with a 16.384 MHz external clock. Each of these
sampling rates preserves the same sampling rate in the ADC’s
sigma-delta modulator, which ensures that the noise perfor-
mance is optimized in each case. The examples below will show
the performance of a 1 kHz sine wave when converted at the
various sample rates.
The range of sampling rates is aimed to offer the user a degree
of flexibility in deciding how their analog front end is to be
implemented. The high sample rates of 64 kHz and 32 kHz are
suited to those applications, such as active control, where low
conversion group delay is essential. On the other hand, the lower
sample rates of 16 kHz and 8 kHz are better suited for appli-
cations such as telephony, where the lower sample rates result
in lower DSP overhead.
Figure 20 shows the spectrum of the 1 kHz test tone sampled at
64 kHz. The plot shows the characteristic shaped noise floor of
a sigma-delta converter, which is initially flat in the band of
interest but then rises with increasing frequency. If a suitable
digital filter is applied to this spectrum, it is possible to eliminate
the noise floor in the higher frequencies. This signal can then be
used in DSP algorithms or can be further processed in a deci-
mation algorithm to reduce the effective sample rate. Figure 17
shows the resulting spectrum following the filtering and decima-
tion of the spectrum of Figure 16 from 64 kHz to an 8 kHz rate.
Table XXI. Device Count Settings
DC1
0
0
1
1
0
0
1
1
DC0
0
1
0
1
0
1
0
1
Cascade Length
1
2
3
4
5
6
7
8
The AD73322L also features direct sampling at the lower rate
of 8 kHz. This is achieved by the use of extended decimation
registers within the decimator block, which allows for the
increased word growth associated with the higher effective
oversampling ratio. Figure 18 details the spectrum of a 1 kHz
test tone converted at an 8 kHz rate.
–100
–120
–140
–100
–120
100
150
–20
–40
–60
–80
–20
–40
–60
–80
50
0
0
0
0
0
0
500
500
0.5
1000
1000
1.0
1500
1500
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
1.5
2000
2000
2.0
2500
2500
2.5
3000
3000
3500
3500
3.0
10
4000
4000
3.5
4