LTC2431CMS#PBF Linear Technology, LTC2431CMS#PBF Datasheet - Page 16

• Manufacturer Part Number: LTC2431CMS#PBF
• Description: IC ADC 20BIT DIFFINPUT/REF10MSOP
• Manufacturer: Linear Technology

Specifications of LTC2431CMS#PBF

• Number Of Bits: 20
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
LTC2430/LTC2431
Table 4. LTC2430/LTC2431 Interface Timing Modes
Configuration
External SCK, Single Cycle Conversion
External SCK, 2-Wire I/O
Internal SCK, Single Cycle Conversion
Internal SCK, 2-Wire I/O, Continuous Conversion
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is over. With CS HIGH, the device auto-
matically enters the low power sleep state once the con-
version is complete.
When CS is low, the device enters the data output mode.
The result is held in the internal static shift register until
the first SCK rising edge is seen while CS is LOW. Data is
shifted out the SDO pin on each falling edge of SCK. This
16
(EXTERNAL)
SDO
SCK
CS
Hi-Z
CONVERSION
TEST EOC
U
SLEEP
TEST EOC
TEST EOC
U
SLEEP
Hi-Z
W
Figure 5. External Serial Clock, Single Cycle Operation
ANALOG INPUT RANGE
–0.5V
BIT 23
EOC
REF
0.1V TO V
REFERENCE
TO 0.5V
BIT 22
VOLTAGE
1 F
U
External
External
2.7V TO 5.5V
Internal
Internal
Source
REF
SCK
CC
BIT 21
SIG
V
REF
REF
IN
IN
GND
CC
+
–
LTC2430/
LTC2431
+
–
BIT 20
MSB
SDO
SCK
enables external circuitry to latch the output on the rising
edge of SCK. EOC can be latched on the first rising edge
of SCK and the last bit of the conversion result can be
latched on the 24th rising edge of SCK. On the 24th falling
edge of SCK, the device begins a new conversion. SDO
goes HIGH (EOC = 1) indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the 24th
falling edge of SCK, see Figure 6. On the rising edge of CS,
CS
F
O
Conversion
CS and SCK
Continuous
Control
BIT 19
Cycle
CS
SCK
DATA OUTPUT
3-WIRE
SPI INTERFACE
V
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
BIT 18
CS and SCK
Control
Internal
Output
CS
Data
SCK
BIT 0
LSB
CONVERSION
Hi-Z
TEST EOC
Connection
Waveforms
Figures 5, 6
Figures 8, 9
Figure 10
2431 F05
Figure 7
and
24301f